| /kernel/liteos_m/arch/arm/cortex-m33/gcc/TZ/secure/ |
| H A D | los_secure_context_asm.S | 63 MSR PSPLIM, R0
64 MSR PSP, R0
66 MSR CONTROL, R0
79 MSR PSPLIM, R2 /* Restore PSPLIM. */
80 MSR PSP, R1 /* Restore PSP. */
95 MSR PSPLIM, R0 /* No PSPLIM for the current task. */
96 MSR PSP, R0 /* No secure stack for the current task. */
|
| /kernel/liteos_m/arch/arm/cortex-m33/iar/TZ/secure/ |
| H A D | los_secure_context_asm.S | 61 MSR PSPLIM, R0
62 MSR PSP, R0
64 MSR CONTROL, R0
72 MSR PSPLIM, R2 /* Restore PSPLIM. */
73 MSR PSP, R1 /* Restore PSP. */
83 MSR PSPLIM, R0 /* No PSPLIM for the current task. */
84 MSR PSP, R0 /* No secure stack for the current task. */
|
| /kernel/liteos_m/arch/arm/cortex-m55/gcc/TZ/secure/ |
| H A D | los_secure_context_asm.S | 63 MSR PSPLIM, R0
64 MSR PSP, R0
66 MSR CONTROL, R0
79 MSR PSPLIM, R2 /* Restore PSPLIM. */
80 MSR PSP, R1 /* Restore PSP. */
95 MSR PSPLIM, R0 /* No PSPLIM for the current task. */
96 MSR PSP, R0 /* No secure stack for the current task. */
|
| /kernel/liteos_m/arch/arm/cortex-m55/iar/TZ/secure/ |
| H A D | los_secure_context_asm.S | 61 MSR PSPLIM, R0
62 MSR PSP, R0
64 MSR CONTROL, R0
72 MSR PSPLIM, R2 /* Restore PSPLIM. */
73 MSR PSP, R1 /* Restore PSP. */
83 MSR PSPLIM, R0 /* No PSPLIM for the current task. */
84 MSR PSP, R0 /* No secure stack for the current task. */
|
| /kernel/liteos_m/arch/arm/arm9/gcc/ |
| H A D | reset_vector.S | 87 MSR CPSR, R0
91 MSR CPSR, R0
95 MSR CPSR, R0
99 MSR CPSR, R0
103 MSR CPSR, R0
104 MSR SPSR, R0
|
| H A D | los_dispatch.S | 106 MSR SPSR_cxsf, R0
112 MSR SPSR_cxsf, R0
120 MSR CPSR, R0
138 MSR SPSR_cxsf, R0
|
| H A D | los_exc.S | 99 MSR CPSR_c, #(OS_PSR_INT_DIS | OS_PSR_MODE_SVC)
123 MSR CPSR, R1
|
| /kernel/uniproton/src/arch/cpu/armv7-m/cortex-m4/ |
| H A D | prt_dispatch.S | 106 MSR MSP, R0
111 MSR CONTROL, R0
139 MSR PSP, R1
141 MSR xPSR, R4
156 MSR BASEPRI, R1
162 MSR BASEPRI, R1
166 MSR BASEPRI, R0
211 MSR BASEPRI, R2
315 MSR PSP, R1
318 MSR BASEPR
[all...] |
| /kernel/liteos_m/arch/arm/cortex-m3/keil/ |
| H A D | los_dispatch.S | 59 MSR CONTROL, R0
69 MSR PSP, R12
74 ;MSR xPSR, R7
91 MSR PRIMASK, R0
113 MSR PRIMASK, R12
133 MSR PSP, R1
135 MSR PRIMASK, R12
|
| /kernel/liteos_m/arch/arm/cortex-m33/iar/TZ/non_secure/ |
| H A D | los_dispatch.S | 76 MSR CONTROL, R0
85 MSR PSPLIM, R2 /* Set the stackLmit for the PSPLIM about current task. */
99 MSR PSP, R12
114 MSR PRIMASK, R0
138 MSR PRIMASK, R12
179 MSR PSPLIM, R2
199 MSR PSP, R1
201 MSR PRIMASK, R12
|
| /kernel/liteos_m/arch/arm/cortex-m55/iar/TZ/non_secure/ |
| H A D | los_dispatch.S | 76 MSR CONTROL, R0
85 MSR PSPLIM, R2 /* Set the stackLmit for the PSPLIM about current task. */
99 MSR PSP, R12
114 MSR PRIMASK, R0
138 MSR PRIMASK, R12
179 MSR PSPLIM, R2
199 MSR PSP, R1
201 MSR PRIMASK, R12
|
| /kernel/liteos_m/arch/arm/cortex-m33/gcc/TZ/non_secure/ |
| H A D | los_dispatch.S | 61 MSR CONTROL, R0
70 MSR PSPLIM, R2 /* Set the stackLmit for the PSPLIM about current task. */
84 MSR PSP, R12
116 MSR PRIMASK, R0
193 MSR PSPLIM, R2
213 MSR PSP, R1
215 MSR PRIMASK, R12
|
| /kernel/liteos_m/arch/arm/cortex-m33/iar/NTZ/ |
| H A D | los_dispatch.S | 71 MSR CONTROL, R0
86 MSR PSP, R12
97 MSR PSP, R12
114 MSR PRIMASK, R0
136 MSR PRIMASK, R12
170 MSR PSP, R1
172 MSR PRIMASK, R12
|
| /kernel/liteos_m/arch/arm/cortex-m4/iar/ |
| H A D | los_dispatch.S | 71 MSR CONTROL, R0
86 MSR PSP, R12
97 MSR PSP, R12
114 MSR PRIMASK, R0
138 MSR PRIMASK, R12
172 MSR PSP, R1
174 MSR PRIMASK, R12
|
| /kernel/liteos_m/arch/arm/cortex-m55/gcc/TZ/non_secure/ |
| H A D | los_dispatch.S | 61 MSR CONTROL, R0
70 MSR PSPLIM, R2 /* Set the stackLmit for the PSPLIM about current task. */
84 MSR PSP, R12
116 MSR PRIMASK, R0
193 MSR PSPLIM, R2
213 MSR PSP, R1
215 MSR PRIMASK, R12
|
| /kernel/liteos_m/arch/arm/cortex-m55/iar/NTZ/ |
| H A D | los_dispatch.S | 71 MSR CONTROL, R0
86 MSR PSP, R12
97 MSR PSP, R12
114 MSR PRIMASK, R0
136 MSR PRIMASK, R12
170 MSR PSP, R1
172 MSR PRIMASK, R12
|
| /kernel/liteos_m/arch/arm/cortex-m7/iar/ |
| H A D | los_dispatch.S | 71 MSR CONTROL, R0
86 MSR PSP, R12
97 MSR PSP, R12
114 MSR PRIMASK, R0
138 MSR PRIMASK, R12
172 MSR PSP, R1
174 MSR PRIMASK, R12
|
| /kernel/liteos_a/arch/arm/arm/src/ |
| H A D | los_hw_exc.S | 111 MSR CPSR_c, R2
119 MSR CPSR_c, R1
143 MSR SPSR, R1
177 MSR CPSR_c, #(CPSR_INT_DISABLE | CPSR_SVC_MODE) @ Switch to svc mode, and disable all interrupt
258 MSR CPSR_c, #(CPSR_INT_DISABLE | CPSR_SVC_MODE) @ Switch to svc mode, and disable all interrupt
300 MSR CPSR_c, #(CPSR_INT_DISABLE | CPSR_SVC_MODE) @ Switch to svc mode, and disable all interrupt
348 MSR CPSR_c, #(CPSR_INT_DISABLE | CPSR_SVC_MODE) @ Switch to svc mode, and disable all interrupt
366 MSR CPSR_c, #(CPSR_INT_DISABLE | CPSR_SVC_MODE) @ Switch to svc mode, and disable all interrupt
|
| H A D | los_hw_runstop.S | 101 MSR CPSR_cxsf, R0
120 MSR SPSR_cxsf, R1
|
| /kernel/linux/linux-5.10/drivers/net/hamradio/ |
| H A D | baycom_ser_hdx.c | 86 #define MSR(iobase) (iobase+6) macro
209 cur_s = inb(MSR(dev->base_addr)) & 0x10; /* the CTS line */ in ser12_rx()
346 hdlcdrv_setdcd(&bc->hdrv, !((inb(MSR(dev->base_addr)) ^ bc->opt_dcd) & 0x80)); in ser12_rx()
398 inb(MSR(dev->base_addr)); in ser12_interrupt()
432 b2 = inb(MSR(iobase)); in ser12_check_uart()
434 b3 = inb(MSR(iobase)) & 0xf0; in ser12_check_uart()
436 outb(b2, MSR(iobase)); in ser12_check_uart()
|
| H A D | baycom_ser_fdx.c | 100 #define MSR(iobase) (iobase+6) macro
262 msr = inb(MSR(dev->base_addr)); in ser12_interrupt()
296 msr = inb(MSR(dev->base_addr)); in ser12_interrupt()
350 b2 = inb(MSR(iobase)); in ser12_check_uart()
352 b3 = inb(MSR(iobase)) & 0xf0; in ser12_check_uart()
354 outb(b2, MSR(iobase)); in ser12_check_uart()
|
| /kernel/linux/linux-6.6/drivers/net/hamradio/ |
| H A D | baycom_ser_hdx.c | 86 #define MSR(iobase) (iobase+6) macro
209 cur_s = inb(MSR(dev->base_addr)) & 0x10; /* the CTS line */ in ser12_rx()
346 hdlcdrv_setdcd(&bc->hdrv, !((inb(MSR(dev->base_addr)) ^ bc->opt_dcd) & 0x80)); in ser12_rx()
398 inb(MSR(dev->base_addr)); in ser12_interrupt()
432 b2 = inb(MSR(iobase)); in ser12_check_uart()
434 b3 = inb(MSR(iobase)) & 0xf0; in ser12_check_uart()
436 outb(b2, MSR(iobase)); in ser12_check_uart()
|
| H A D | baycom_ser_fdx.c | 100 #define MSR(iobase) (iobase+6) macro
262 msr = inb(MSR(dev->base_addr)); in ser12_interrupt()
296 msr = inb(MSR(dev->base_addr)); in ser12_interrupt()
350 b2 = inb(MSR(iobase)); in ser12_check_uart()
352 b3 = inb(MSR(iobase)) & 0xf0; in ser12_check_uart()
354 outb(b2, MSR(iobase)); in ser12_check_uart()
|
| /kernel/linux/linux-5.10/arch/sparc/include/asm/ |
| H A D | floppy_64.h | 448 #define MSR (port + 4) macro
457 while (!((status = inb(MSR)) & 0x80) && --timeout) in sun_pci_fd_out_byte()
472 while (!((status = inb(MSR)) & 0x80) && --timeout) in sun_pci_fd_sensei()
493 outb(0x80, MSR); in sun_pci_fd_reset()
531 #undef MSR macro
|
| /kernel/linux/linux-6.6/arch/sparc/include/asm/ |
| H A D | floppy_64.h | 448 #define MSR (port + 4) macro
457 while (!((status = inb(MSR)) & 0x80) && --timeout) in sun_pci_fd_out_byte()
472 while (!((status = inb(MSR)) & 0x80) && --timeout) in sun_pci_fd_sensei()
493 outb(0x80, MSR); in sun_pci_fd_reset()
531 #undef MSR macro
|