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Searched refs:MP1_C2PMSG_90__CONTENT_MASK (Results 1 - 16 of 16) sorted by relevance

/kernel/linux/linux-5.10/drivers/gpu/drm/amd/pm/powerplay/smumgr/
H A Dsmu9_smumgr.c78 0, MP1_C2PMSG_90__CONTENT_MASK); in smu9_wait_for_response()
H A Dsmu10_smumgr.c57 0, MP1_C2PMSG_90__CONTENT_MASK); in smu10_wait_for_response()
H A Dvega20_smumgr.c78 0, MP1_C2PMSG_90__CONTENT_MASK); in vega20_wait_for_response()
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/pm/powerplay/smumgr/
H A Dsmu9_smumgr.c79 0, MP1_C2PMSG_90__CONTENT_MASK); in smu9_wait_for_response()
H A Dsmu10_smumgr.c57 0, MP1_C2PMSG_90__CONTENT_MASK); in smu10_wait_for_response()
H A Dvega20_smumgr.c78 0, MP1_C2PMSG_90__CONTENT_MASK); in vega20_wait_for_response()
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/pm/swsmu/
H A Dsmu_cmn.c54 #define MP1_C2PMSG_90__CONTENT_MASK 0xFFFFFFFFL macro
94 if ((cur_value & MP1_C2PMSG_90__CONTENT_MASK) != 0) in smu_cmn_wait_for_response()
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/pm/swsmu/
H A Dsmu_cmn.c40 #define MP1_C2PMSG_90__CONTENT_MASK 0xFFFFFFFFL macro
117 if ((reg & MP1_C2PMSG_90__CONTENT_MASK) != 0) in __smu_cmn_poll_stat()
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/mp/
H A Dmp_11_0_sh_mask.h602 #define MP1_C2PMSG_90__CONTENT_MASK 0xFFFFFFFFL macro
H A Dmp_10_0_sh_mask.h821 #define MP1_C2PMSG_90__CONTENT_MASK 0xFFFFFFFFL macro
H A Dmp_12_0_0_sh_mask.h806 #define MP1_C2PMSG_90__CONTENT_MASK 0xFFFFFFFFL macro
H A Dmp_9_0_sh_mask.h1371 #define MP1_C2PMSG_90__CONTENT_MASK 0xFFFFFFFFL macro
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/include/asic_reg/mp/
H A Dmp_11_0_sh_mask.h602 #define MP1_C2PMSG_90__CONTENT_MASK 0xFFFFFFFFL macro
H A Dmp_10_0_sh_mask.h821 #define MP1_C2PMSG_90__CONTENT_MASK 0xFFFFFFFFL macro
H A Dmp_12_0_0_sh_mask.h806 #define MP1_C2PMSG_90__CONTENT_MASK 0xFFFFFFFFL macro
H A Dmp_9_0_sh_mask.h1371 #define MP1_C2PMSG_90__CONTENT_MASK 0xFFFFFFFFL macro

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