| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/ |
| H A D | rv1_clk_mgr_vbios_smu.c | 43 static const struct IP_BASE MP1_BASE = { { { { 0x00016000, 0, 0, 0, 0 } }, variable
64 (MP1_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name)
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| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/ |
| H A D | rv1_clk_mgr_vbios_smu.c | 45 static const struct IP_BASE MP1_BASE = { { { { 0x00016000, 0, 0, 0, 0 } }, variable
66 (MP1_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name)
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| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/amdgpu/ |
| H A D | navi12_reg_init.c | 40 adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i])); in navi12_reg_base_init()
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| H A D | navi14_reg_init.c | 40 adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i])); in navi14_reg_base_init()
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| H A D | navi10_reg_init.c | 40 adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i])); in navi10_reg_base_init()
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| H A D | sienna_cichlid_reg_init.c | 41 adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i])); in sienna_cichlid_reg_base_init()
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| H A D | arct_reg_init.c | 40 adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i])); in arct_reg_base_init()
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| H A D | vega20_reg_init.c | 40 adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i])); in vega20_reg_base_init()
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| H A D | vega10_reg_init.c | 40 adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i])); in vega10_reg_base_init()
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| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/amdgpu/ |
| H A D | aldebaran_reg_init.c | 40 adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i])); in aldebaran_reg_base_init()
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| H A D | dimgrey_cavefish_reg_init.c | 41 adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i])); in dimgrey_cavefish_reg_base_init()
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| H A D | arct_reg_init.c | 40 adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i])); in arct_reg_base_init()
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| H A D | vega20_reg_init.c | 40 adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i])); in vega20_reg_base_init()
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| H A D | vega10_reg_init.c | 40 adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i])); in vega10_reg_base_init()
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| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/include/ |
| H A D | cyan_skillfish_ip_offset.h | 93 static const struct IP_BASE MP1_BASE ={ { { { 0x00016000, 0, 0, 0, 0 } }, variable
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| H A D | navi12_ip_offset.h | 123 static const struct IP_BASE MP1_BASE ={ { { { 0x00016000, 0x00E80000, 0x00EC0000, 0x00F00000, 0x02400400 } }, variable
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| H A D | navi14_ip_offset.h | 123 static const struct IP_BASE MP1_BASE ={ { { { 0x00016000, 0x00DC0000, 0x00E00000, 0x00E40000, 0x0243FC00 } }, variable
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| H A D | vega20_ip_offset.h | 93 static const struct IP_BASE MP1_BASE ={ { { { 0x00016000, 0, 0, 0, 0, 0 } }, variable
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| H A D | navi10_ip_offset.h | 91 static const struct IP_BASE MP1_BASE ={ { { { 0x00016000, 0, 0, 0, 0, 0 } }, variable
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| H A D | dimgrey_cavefish_ip_offset.h | 116 static const struct IP_BASE MP1_BASE = { { { { 0x00016200, 0x00E80000, 0x00EC0000, 0x00F00000, 0x02400400, 0 } }, variable
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| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/include/ |
| H A D | navi12_ip_offset.h | 123 static const struct IP_BASE MP1_BASE ={ { { { 0x00016000, 0x00E80000, 0x00EC0000, 0x00F00000, 0x02400400 } }, variable
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| H A D | navi14_ip_offset.h | 123 static const struct IP_BASE MP1_BASE ={ { { { 0x00016000, 0x00DC0000, 0x00E00000, 0x00E40000, 0x0243FC00 } }, variable
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| H A D | navi10_ip_offset.h | 91 static const struct IP_BASE MP1_BASE ={ { { { 0x00016000, 0, 0, 0, 0, 0 } }, variable
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| H A D | vega20_ip_offset.h | 93 static const struct IP_BASE MP1_BASE ={ { { { 0x00016000, 0, 0, 0, 0, 0 } }, variable
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| H A D | renoir_ip_offset.h | 158 static const struct IP_BASE MP1_BASE ={ { { { 0x00016000, 0x02400400, 0x00E80000, 0x00EC0000, 0x00F00000 } }, variable
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