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Searched refs:MMSCH_V1_0_INSERT_DIRECT_WT (Results 1 - 8 of 8) sorted by relevance

/kernel/linux/linux-5.10/drivers/gpu/drm/amd/amdgpu/
H A Dvce_v4_0.c233 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_BASE_LO), in vce_v4_0_sriov_start()
235 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_BASE_HI), in vce_v4_0_sriov_start()
237 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_SIZE), in vce_v4_0_sriov_start()
241 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_CTRL), 0x398000); in vce_v4_0_sriov_start()
243 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_SWAP_CNTL), 0); in vce_v4_0_sriov_start()
244 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_SWAP_CNTL1), 0); in vce_v4_0_sriov_start()
245 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VM_CTRL), 0); in vce_v4_0_sriov_start()
253 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, in vce_v4_0_sriov_start()
255 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, in vce_v4_0_sriov_start()
258 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSE in vce_v4_0_sriov_start()
[all...]
H A Duvd_v7_0.c803 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, in uvd_v7_0_sriov_start()
806 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, in uvd_v7_0_sriov_start()
809 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 0); in uvd_v7_0_sriov_start()
812 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), in uvd_v7_0_sriov_start()
814 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), in uvd_v7_0_sriov_start()
817 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), in uvd_v7_0_sriov_start()
822 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE0), size); in uvd_v7_0_sriov_start()
824 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), in uvd_v7_0_sriov_start()
826 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), in uvd_v7_0_sriov_start()
828 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSE in uvd_v7_0_sriov_start()
[all...]
H A Dvcn_v2_5.c1197 MMSCH_V1_0_INSERT_DIRECT_WT( in vcn_v2_5_sriov_start()
1201 MMSCH_V1_0_INSERT_DIRECT_WT( in vcn_v2_5_sriov_start()
1206 MMSCH_V1_0_INSERT_DIRECT_WT( in vcn_v2_5_sriov_start()
1209 MMSCH_V1_0_INSERT_DIRECT_WT( in vcn_v2_5_sriov_start()
1213 MMSCH_V1_0_INSERT_DIRECT_WT( in vcn_v2_5_sriov_start()
1218 MMSCH_V1_0_INSERT_DIRECT_WT( in vcn_v2_5_sriov_start()
1223 MMSCH_V1_0_INSERT_DIRECT_WT( in vcn_v2_5_sriov_start()
1226 MMSCH_V1_0_INSERT_DIRECT_WT( in vcn_v2_5_sriov_start()
1230 MMSCH_V1_0_INSERT_DIRECT_WT( in vcn_v2_5_sriov_start()
1234 MMSCH_V1_0_INSERT_DIRECT_WT( in vcn_v2_5_sriov_start()
[all...]
H A Dmmsch_v1_0.h140 #define MMSCH_V1_0_INSERT_DIRECT_WT(reg, value) { \ macro
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/amdgpu/
H A Dvce_v4_0.c234 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_BASE_LO), in vce_v4_0_sriov_start()
236 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_BASE_HI), in vce_v4_0_sriov_start()
238 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_SIZE), in vce_v4_0_sriov_start()
242 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_CTRL), 0x398000); in vce_v4_0_sriov_start()
244 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_SWAP_CNTL), 0); in vce_v4_0_sriov_start()
245 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_SWAP_CNTL1), 0); in vce_v4_0_sriov_start()
246 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VM_CTRL), 0); in vce_v4_0_sriov_start()
254 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, in vce_v4_0_sriov_start()
256 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, in vce_v4_0_sriov_start()
259 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSE in vce_v4_0_sriov_start()
[all...]
H A Duvd_v7_0.c824 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, in uvd_v7_0_sriov_start()
827 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, in uvd_v7_0_sriov_start()
830 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 0); in uvd_v7_0_sriov_start()
833 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), in uvd_v7_0_sriov_start()
835 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), in uvd_v7_0_sriov_start()
838 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), in uvd_v7_0_sriov_start()
843 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE0), size); in uvd_v7_0_sriov_start()
845 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), in uvd_v7_0_sriov_start()
847 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), in uvd_v7_0_sriov_start()
849 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSE in uvd_v7_0_sriov_start()
[all...]
H A Dvcn_v2_5.c1245 MMSCH_V1_0_INSERT_DIRECT_WT( in vcn_v2_5_sriov_start()
1249 MMSCH_V1_0_INSERT_DIRECT_WT( in vcn_v2_5_sriov_start()
1254 MMSCH_V1_0_INSERT_DIRECT_WT( in vcn_v2_5_sriov_start()
1257 MMSCH_V1_0_INSERT_DIRECT_WT( in vcn_v2_5_sriov_start()
1261 MMSCH_V1_0_INSERT_DIRECT_WT( in vcn_v2_5_sriov_start()
1266 MMSCH_V1_0_INSERT_DIRECT_WT( in vcn_v2_5_sriov_start()
1271 MMSCH_V1_0_INSERT_DIRECT_WT( in vcn_v2_5_sriov_start()
1274 MMSCH_V1_0_INSERT_DIRECT_WT( in vcn_v2_5_sriov_start()
1278 MMSCH_V1_0_INSERT_DIRECT_WT( in vcn_v2_5_sriov_start()
1282 MMSCH_V1_0_INSERT_DIRECT_WT( in vcn_v2_5_sriov_start()
[all...]
H A Dmmsch_v1_0.h138 #define MMSCH_V1_0_INSERT_DIRECT_WT(reg, value) { \ macro

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