| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/amdgpu/ |
| H A D | mmhub_v2_0.c | 154 switch (adev->ip_versions[MMHUB_HWIP][0]) { in mmhub_v2_0_print_l2_protection_fault_status()
571 switch (adev->ip_versions[MMHUB_HWIP][0]) { in mmhub_v2_0_update_medium_grain_clock_gating()
604 switch (adev->ip_versions[MMHUB_HWIP][0]) { in mmhub_v2_0_update_medium_grain_clock_gating()
628 switch (adev->ip_versions[MMHUB_HWIP][0]) { in mmhub_v2_0_update_medium_grain_light_sleep()
654 switch (adev->ip_versions[MMHUB_HWIP][0]) { in mmhub_v2_0_set_clockgating()
679 switch (adev->ip_versions[MMHUB_HWIP][0]) { in mmhub_v2_0_get_clockgating()
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| H A D | aldebaran_reg_init.c | 36 adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i])); in aldebaran_reg_base_init()
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| H A D | dimgrey_cavefish_reg_init.c | 37 adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i])); in dimgrey_cavefish_reg_base_init()
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| H A D | arct_reg_init.c | 36 adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i])); in arct_reg_base_init()
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| H A D | vega20_reg_init.c | 36 adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i])); in vega20_reg_base_init()
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| H A D | vega10_reg_init.c | 36 adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i])); in vega10_reg_base_init()
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| H A D | amdgpu_discovery.c | 188 [MMHUB_HWIP] = MMHUB_HWID,
2163 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 0, 0); in amdgpu_discovery_set_ip_blocks()
2185 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 3, 0); in amdgpu_discovery_set_ip_blocks()
2209 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 2, 0); in amdgpu_discovery_set_ip_blocks()
2225 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 1, 0); in amdgpu_discovery_set_ip_blocks()
2246 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 0); in amdgpu_discovery_set_ip_blocks()
2270 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 1); in amdgpu_discovery_set_ip_blocks()
2298 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 2); in amdgpu_discovery_set_ip_blocks()
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| H A D | gmc_v10_0.c | 246 GC_HWIP : MMHUB_HWIP; in gmc_v10_0_flush_vm_hub()
700 switch (adev->ip_versions[MMHUB_HWIP][0]) { in gmc_v10_0_set_mmhub_funcs()
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| H A D | gmc_v11_0.c | 207 GC_HWIP : MMHUB_HWIP; in gmc_v11_0_flush_vm_hub()
613 switch (adev->ip_versions[MMHUB_HWIP][0]) { in gmc_v11_0_set_mmhub_funcs()
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| H A D | gmc_v9_0.c | 673 switch (adev->ip_versions[MMHUB_HWIP][0]) { in gmc_v9_0_process_interrupt()
1500 switch (adev->ip_versions[MMHUB_HWIP][0]) { in gmc_v9_0_set_mmhub_funcs()
1518 switch (adev->ip_versions[MMHUB_HWIP][0]) { in gmc_v9_0_set_mmhub_ras_funcs()
2245 switch (adev->ip_versions[MMHUB_HWIP][0]) { in gmc_v9_0_init_golden_registers()
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| H A D | mmhub_v3_0_1.c | 111 switch (adev->ip_versions[MMHUB_HWIP][0]) { in mmhub_v3_0_1_print_l2_protection_fault_status()
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| H A D | mmhub_v3_0.c | 110 switch (adev->ip_versions[MMHUB_HWIP][0]) { in mmhub_v3_0_print_l2_protection_fault_status()
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| H A D | mmhub_v2_3.c | 93 switch (adev->ip_versions[MMHUB_HWIP][0]) { in mmhub_v2_3_print_l2_protection_fault_status()
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| H A D | amdgpu.h | 647 MMHUB_HWIP, enumerator
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| H A D | mes_v11_0.c | 397 adev->reg_offset[MMHUB_HWIP][0][i]; in mes_v11_0_set_hw_resources()
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| H A D | mes_v10_1.c | 306 adev->reg_offset[MMHUB_HWIP][0][i]; in mes_v10_1_set_hw_resources()
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| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/amdgpu/ |
| H A D | navi12_reg_init.c | 36 adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i])); in navi12_reg_base_init()
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| H A D | navi14_reg_init.c | 36 adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i])); in navi14_reg_base_init()
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| H A D | navi10_reg_init.c | 36 adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i])); in navi10_reg_base_init()
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| H A D | sienna_cichlid_reg_init.c | 37 adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i])); in sienna_cichlid_reg_base_init()
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| H A D | arct_reg_init.c | 36 adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i])); in arct_reg_base_init()
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| H A D | vega20_reg_init.c | 36 adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i])); in vega20_reg_base_init()
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| H A D | vega10_reg_init.c | 36 adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i])); in vega10_reg_base_init()
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| H A D | amdgpu_discovery.c | 116 [MMHUB_HWIP] = MMHUB_HWID,
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| H A D | amdgpu.h | 698 MMHUB_HWIP, enumerator
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