| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/amdgpu/ |
| H A D | navi12_reg_init.c | 36 adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i])); in navi12_reg_base_init()
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| H A D | navi14_reg_init.c | 36 adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i])); in navi14_reg_base_init()
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| H A D | navi10_reg_init.c | 36 adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i])); in navi10_reg_base_init()
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| H A D | sienna_cichlid_reg_init.c | 37 adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i])); in sienna_cichlid_reg_base_init()
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| H A D | arct_reg_init.c | 36 adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i])); in arct_reg_base_init()
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| H A D | vega20_reg_init.c | 36 adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i])); in vega20_reg_base_init()
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| H A D | vega10_reg_init.c | 36 adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i])); in vega10_reg_base_init()
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| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/amdgpu/ |
| H A D | aldebaran_reg_init.c | 36 adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i])); in aldebaran_reg_base_init()
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| H A D | dimgrey_cavefish_reg_init.c | 37 adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i])); in dimgrey_cavefish_reg_base_init()
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| H A D | arct_reg_init.c | 36 adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i])); in arct_reg_base_init()
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| H A D | vega20_reg_init.c | 36 adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i])); in vega20_reg_base_init()
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| H A D | vega10_reg_init.c | 36 adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i])); in vega10_reg_base_init()
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| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/include/ |
| H A D | cyan_skillfish_ip_offset.h | 81 static const struct IP_BASE MMHUB_BASE ={ { { { 0x0001A000, 0, 0, 0, 0 } }, variable
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| H A D | navi12_ip_offset.h | 109 static const struct IP_BASE MMHUB_BASE ={ { { { 0x0001A000, 0x02408800, 0, 0, 0 } }, variable
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| H A D | navi14_ip_offset.h | 109 static const struct IP_BASE MMHUB_BASE ={ { { { 0x0001A000, 0x02408800, 0, 0, 0 } }, variable
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| H A D | vega20_ip_offset.h | 81 static const struct IP_BASE MMHUB_BASE ={ { { { 0x0001A000, 0, 0, 0, 0, 0 } }, variable
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| H A D | navi10_ip_offset.h | 79 static const struct IP_BASE MMHUB_BASE ={ { { { 0x0001A000, 0, 0, 0, 0, 0 } }, variable
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| H A D | dimgrey_cavefish_ip_offset.h | 102 static const struct IP_BASE MMHUB_BASE = { { { { 0x0001A000, 0x02408800, 0, 0, 0, 0 } }, variable
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| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/include/ |
| H A D | navi12_ip_offset.h | 109 static const struct IP_BASE MMHUB_BASE ={ { { { 0x0001A000, 0x02408800, 0, 0, 0 } }, variable
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| H A D | navi14_ip_offset.h | 109 static const struct IP_BASE MMHUB_BASE ={ { { { 0x0001A000, 0x02408800, 0, 0, 0 } }, variable
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| H A D | navi10_ip_offset.h | 79 static const struct IP_BASE MMHUB_BASE ={ { { { 0x0001A000, 0, 0, 0, 0, 0 } }, variable
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| H A D | vega20_ip_offset.h | 81 static const struct IP_BASE MMHUB_BASE ={ { { { 0x0001A000, 0, 0, 0, 0, 0 } }, variable
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| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dce120/ |
| H A D | dce120_resource.c | 150 #define MMHUB_BASE(seg) \ macro
154 .reg_name = MMHUB_BASE(mm ## reg_name ## _BASE_IDX) + \
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| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dcn10/ |
| H A D | dcn10_resource.c | 208 #define MMHUB_BASE(seg) \ macro
212 .reg_name = MMHUB_BASE(mm ## reg_name ## _BASE_IDX) + \
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| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dce120/ |
| H A D | dce120_resource.c | 148 #define MMHUB_BASE(seg) \ macro
152 .reg_name = MMHUB_BASE(mm ## reg_name ## _BASE_IDX) + \
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