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Searched refs:MMCIPOWER (Results 1 - 6 of 6) sorted by relevance

/kernel/linux/linux-5.10/drivers/mmc/host/
H A Dmmci.h7 #define MMCIPOWER 0x000 macro
294 * @pwrreg_powerup: power up value for MMCIPOWER register
297 * @pwrreg_clkgate: MMCIPOWER register must be used to gate the clock
306 * @pwrreg_nopower: bits in MMCIPOWER don't controls ext. power supply
316 * @opendrain: bitmask identifying the OPENDRAIN bit inside MMCIPOWER register
H A Dmmci.c354 * Three MCLK clock cycles must pass between two MMCIPOWER reg writes. in mmci_reg_delay()
382 writel(pwr, host->base + MMCIPOWER); in mmci_write_pwrreg()
1679 writel(host->pwr_reg, host->base + MMCIPOWER); in mmci_irq_thread()
1817 * If clock = 0 and the variant requires the MMCIPOWER to be used for in mmci_set_ios()
2249 writel(0, host->base + MMCIPOWER); in mmci_save()
2266 writel(host->pwr_reg, host->base + MMCIPOWER); in mmci_restore()
H A Dmmci_stm32_sdmmc.c529 host->pwr_reg = readl_relaxed(host->base + MMCIPOWER); in sdmmc_variant_init()
/kernel/linux/linux-6.6/drivers/mmc/host/
H A Dmmci.h7 #define MMCIPOWER 0x000 macro
310 * @pwrreg_powerup: power up value for MMCIPOWER register
313 * @pwrreg_clkgate: MMCIPOWER register must be used to gate the clock
322 * @pwrreg_nopower: bits in MMCIPOWER don't controls ext. power supply
332 * @opendrain: bitmask identifying the OPENDRAIN bit inside MMCIPOWER register
H A Dmmci.c386 * Three MCLK clock cycles must pass between two MMCIPOWER reg writes. in mmci_reg_delay()
414 writel(pwr, host->base + MMCIPOWER); in mmci_write_pwrreg()
1841 writel(host->pwr_reg, host->base + MMCIPOWER); in mmci_irq_thread()
1975 * If clock = 0 and the variant requires the MMCIPOWER to be used for in mmci_set_ios()
2473 writel(0, host->base + MMCIPOWER); in mmci_save()
2490 writel(host->pwr_reg, host->base + MMCIPOWER); in mmci_restore()
H A Dmmci_stm32_sdmmc.c730 host->pwr_reg = readl_relaxed(host->base + MMCIPOWER); in sdmmc_variant_init()

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