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Searched refs:MI_FLUSH_DW_USE_GTT (Results 1 - 9 of 9) sorted by relevance

/kernel/linux/linux-5.10/drivers/gpu/drm/i915/gt/
H A Dgen6_engine_cs.c204 *cs++ = HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT; in mi_flush_dw()
380 *cs++ = I915_GEM_HWS_SEQNO_ADDR | MI_FLUSH_DW_USE_GTT; in gen6_emit_breadcrumb_xcs()
401 *cs++ = I915_GEM_HWS_SEQNO_ADDR | MI_FLUSH_DW_USE_GTT; in gen7_emit_breadcrumb_xcs()
H A Dintel_gpu_commands.h154 #define MI_FLUSH_DW_USE_GTT (1<<2) macro
H A Dintel_engine.h307 gtt_offset | MI_FLUSH_DW_USE_GTT, in gen8_emit_ggtt_write()
/kernel/linux/linux-6.6/drivers/gpu/drm/i915/gt/
H A Dgen6_engine_cs.c205 *cs++ = HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT; in mi_flush_dw()
381 *cs++ = I915_GEM_HWS_SEQNO_ADDR | MI_FLUSH_DW_USE_GTT; in gen6_emit_breadcrumb_xcs()
402 *cs++ = I915_GEM_HWS_SEQNO_ADDR | MI_FLUSH_DW_USE_GTT; in gen7_emit_breadcrumb_xcs()
H A Dgen8_engine_cs.h138 gtt_offset | MI_FLUSH_DW_USE_GTT, in gen8_emit_ggtt_write()
H A Dintel_gpu_commands.h174 #define MI_FLUSH_DW_USE_GTT (1<<2) macro
/kernel/linux/linux-6.6/drivers/gpu/drm/i915/pxp/
H A Dintel_pxp_cmd.c40 *cs++ = I915_GEM_HWS_PXP_ADDR | MI_FLUSH_DW_USE_GTT; in pxp_emit_session_selection()
/kernel/linux/linux-5.10/drivers/gpu/drm/i915/
H A Di915_cmd_parser.c345 .mask = MI_FLUSH_DW_USE_GTT,
389 .mask = MI_FLUSH_DW_USE_GTT,
426 .mask = MI_FLUSH_DW_USE_GTT,
/kernel/linux/linux-6.6/drivers/gpu/drm/i915/
H A Di915_cmd_parser.c354 .mask = MI_FLUSH_DW_USE_GTT,
398 .mask = MI_FLUSH_DW_USE_GTT,
435 .mask = MI_FLUSH_DW_USE_GTT,

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