MII_TG3_DSP_RW_PORT (reference) in projects: kernel - OpenGrok search results

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Searched refs:MII_TG3_DSP_RW_PORT (Results 1 - 4 of 4) sorted by relevance

/kernel/linux/linux-5.10/drivers/net/ethernet/broadcom/
H A D	tg3.c	1286 err = tg3_readphy(tp, MII_TG3_DSP_RW_PORT, val); in tg3_phydsp_read() 1297 err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val); in tg3_phydsp_write() 2482 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, in tg3_phy_write_and_check_testpat() 2508 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) \|\| in tg3_phy_write_and_check_testpat() 2509 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) \|\| in tg3_phy_write_and_check_testpat() 2519 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001); in tg3_phy_write_and_check_testpat() 2520 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005); in tg3_phy_write_and_check_testpat() 2541 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000); in tg3_phy_reset_chanpat() 2729 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b); in tg3_phy_reset() 2733 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, in tg3_phy_reset() [all...]
H A D	tg3.h	`2300 #define MII_TG3_DSP_RW_PORT 0x15 /* DSP coefficient read/write port */ macro`
/kernel/linux/linux-6.6/drivers/net/ethernet/broadcom/
H A D	tg3.c	1287 err = tg3_readphy(tp, MII_TG3_DSP_RW_PORT, val); in tg3_phydsp_read() 1298 err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val); in tg3_phydsp_write() 2476 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, in tg3_phy_write_and_check_testpat() 2502 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) \|\| in tg3_phy_write_and_check_testpat() 2503 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) \|\| in tg3_phy_write_and_check_testpat() 2513 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001); in tg3_phy_write_and_check_testpat() 2514 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005); in tg3_phy_write_and_check_testpat() 2535 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000); in tg3_phy_reset_chanpat() 2723 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b); in tg3_phy_reset() 2727 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, in tg3_phy_reset() [all...]
H A D	tg3.h	`2300 #define MII_TG3_DSP_RW_PORT 0x15 /* DSP coefficient read/write port */ macro`

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