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Searched refs:MII_TG3_DSP_CONTROL (Results 1 - 4 of 4) sorted by relevance

/kernel/linux/linux-5.10/drivers/net/ethernet/broadcom/
H A Dtg3.c2453 if (!tg3_readphy(tp, MII_TG3_DSP_CONTROL, &tmp32)) { in tg3_wait_macro_done()
2479 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002); in tg3_phy_write_and_check_testpat()
2485 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202); in tg3_phy_write_and_check_testpat()
2493 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082); in tg3_phy_write_and_check_testpat()
2499 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802); in tg3_phy_write_and_check_testpat()
2539 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002); in tg3_phy_reset_chanpat()
2542 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202); in tg3_phy_reset_chanpat()
2602 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000); in tg3_phy_reset_5703_4_5()
H A Dtg3.h2301 #define MII_TG3_DSP_CONTROL 0x16 /* DSP control register */ macro
/kernel/linux/linux-6.6/drivers/net/ethernet/broadcom/
H A Dtg3.c2447 if (!tg3_readphy(tp, MII_TG3_DSP_CONTROL, &tmp32)) { in tg3_wait_macro_done()
2473 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002); in tg3_phy_write_and_check_testpat()
2479 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202); in tg3_phy_write_and_check_testpat()
2487 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082); in tg3_phy_write_and_check_testpat()
2493 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802); in tg3_phy_write_and_check_testpat()
2533 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002); in tg3_phy_reset_chanpat()
2536 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202); in tg3_phy_reset_chanpat()
2596 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000); in tg3_phy_reset_5703_4_5()
H A Dtg3.h2301 #define MII_TG3_DSP_CONTROL 0x16 /* DSP control register */ macro

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