MAX_REGULAR_DPM_NUMBER (reference) in projects: kernel

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Searched refs:MAX_REGULAR_DPM_NUMBER (Results 1 - 22 of 22) sorted by relevance

/kernel/linux/linux-5.10/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A D	vega12_hwmgr.h	`96 #define MAX_REGULAR_DPM_NUMBER 16 macro 110 struct vega12_dpm_level dpm_levels[MAX_REGULAR_DPM_NUMBER]; 115 uint32_t entries[MAX_REGULAR_DPM_NUMBER]; 212 struct vega12_mclk_latency_entries entries[MAX_REGULAR_DPM_NUMBER]; 285 entries[MAX_REGULAR_DPM_NUMBER];`
H A D	vega10_hwmgr.h	`122 #define MAX_REGULAR_DPM_NUMBER 8 macro 136 struct vega10_dpm_level dpm_levels[MAX_REGULAR_DPM_NUMBER]; 221 struct vega10_mclk_latency_entries entries[MAX_REGULAR_DPM_NUMBER]; 286 struct phm_ppt_v1_clock_voltage_dependency_record entries[MAX_REGULAR_DPM_NUMBER]; 291 struct phm_ppt_v1_voltage_lookup_record entries[MAX_REGULAR_DPM_NUMBER];`
H A D	smu7_hwmgr.h	`95 #define MAX_REGULAR_DPM_NUMBER 8 macro 100 struct smu7_dpm_level dpm_levels[MAX_REGULAR_DPM_NUMBER]; 179 phm_ppt_v1_clock_voltage_dependency_record entries[MAX_REGULAR_DPM_NUMBER];`
H A D	vega20_hwmgr.h	`139 #define MAX_REGULAR_DPM_NUMBER 16 macro 162 struct vega20_dpm_level dpm_levels[MAX_REGULAR_DPM_NUMBER]; 167 uint32_t entries[MAX_REGULAR_DPM_NUMBER]; 272 struct vega20_mclk_latency_entries entries[MAX_REGULAR_DPM_NUMBER]; 347 entries[MAX_REGULAR_DPM_NUMBER];`
H A D	smu10_hwmgr.h	`175 #define MAX_REGULAR_DPM_NUMBER 8 macro 184 struct smu10_mclk_latency_entries entries[MAX_REGULAR_DPM_NUMBER];`
H A D	smu7_hwmgr.c	`602 MAX_REGULAR_DPM_NUMBER); in smu7_setup_default_pcie_table() 687 MAX_REGULAR_DPM_NUMBER); in smu7_reset_dpm_tables() 691 SMU_MAX_LEVELS_MEMORY), MAX_REGULAR_DPM_NUMBER); in smu7_reset_dpm_tables() 697 MAX_REGULAR_DPM_NUMBER); in smu7_reset_dpm_tables() 701 SMU_MAX_LEVELS_VDDCI), MAX_REGULAR_DPM_NUMBER); in smu7_reset_dpm_tables() 707 MAX_REGULAR_DPM_NUMBER); in smu7_reset_dpm_tables()`
H A D	vega12_hwmgr.c	`1112 PP_ASSERT_WITH_CODE(table->count <= MAX_REGULAR_DPM_NUMBER, in vega12_find_highest_dpm_level() 1114 return MAX_REGULAR_DPM_NUMBER - 1); in vega12_find_highest_dpm_level()`
H A D	vega10_hwmgr.c	`1794 while (i < MAX_REGULAR_DPM_NUMBER) { in vega10_populate_vddc_soc_levels() 3557 if (table->count <= MAX_REGULAR_DPM_NUMBER) { in vega10_find_highest_dpm_level() 3564 return MAX_REGULAR_DPM_NUMBER - 1; in vega10_find_highest_dpm_level()`
H A D	vega20_hwmgr.c	`1801 PP_ASSERT_WITH_CODE(table->count <= MAX_REGULAR_DPM_NUMBER, in vega20_find_highest_dpm_level() 1803 return MAX_REGULAR_DPM_NUMBER - 1); in vega20_find_highest_dpm_level()`
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A D	vega10_hwmgr.h	`122 #define MAX_REGULAR_DPM_NUMBER 8 macro 136 struct vega10_dpm_level dpm_levels[MAX_REGULAR_DPM_NUMBER]; 221 struct vega10_mclk_latency_entries entries[MAX_REGULAR_DPM_NUMBER]; 286 struct phm_ppt_v1_clock_voltage_dependency_record entries[MAX_REGULAR_DPM_NUMBER]; 291 struct phm_ppt_v1_voltage_lookup_record entries[MAX_REGULAR_DPM_NUMBER];`
H A D	vega12_hwmgr.h	`95 #define MAX_REGULAR_DPM_NUMBER 16 macro 109 struct vega12_dpm_level dpm_levels[MAX_REGULAR_DPM_NUMBER]; 114 uint32_t entries[MAX_REGULAR_DPM_NUMBER]; 211 struct vega12_mclk_latency_entries entries[MAX_REGULAR_DPM_NUMBER]; 284 entries[MAX_REGULAR_DPM_NUMBER];`
H A D	smu7_hwmgr.h	`95 #define MAX_REGULAR_DPM_NUMBER 8 macro 100 struct smu7_dpm_level dpm_levels[MAX_REGULAR_DPM_NUMBER]; 179 phm_ppt_v1_clock_voltage_dependency_record entries[MAX_REGULAR_DPM_NUMBER]; 210 struct smu7_mclk_latency_entries entries[MAX_REGULAR_DPM_NUMBER];`
H A D	vega20_hwmgr.h	`139 #define MAX_REGULAR_DPM_NUMBER 16 macro 162 struct vega20_dpm_level dpm_levels[MAX_REGULAR_DPM_NUMBER]; 167 uint32_t entries[MAX_REGULAR_DPM_NUMBER]; 272 struct vega20_mclk_latency_entries entries[MAX_REGULAR_DPM_NUMBER]; 347 entries[MAX_REGULAR_DPM_NUMBER];`
H A D	smu10_hwmgr.h	`175 #define MAX_REGULAR_DPM_NUMBER 8 macro 184 struct smu10_mclk_latency_entries entries[MAX_REGULAR_DPM_NUMBER];`
H A D	smu7_hwmgr.c	`664 MAX_REGULAR_DPM_NUMBER); in smu7_setup_default_pcie_table() 749 MAX_REGULAR_DPM_NUMBER); in smu7_reset_dpm_tables() 753 SMU_MAX_LEVELS_MEMORY), MAX_REGULAR_DPM_NUMBER); in smu7_reset_dpm_tables() 759 MAX_REGULAR_DPM_NUMBER); in smu7_reset_dpm_tables() 763 SMU_MAX_LEVELS_VDDCI), MAX_REGULAR_DPM_NUMBER); in smu7_reset_dpm_tables() 769 MAX_REGULAR_DPM_NUMBER); in smu7_reset_dpm_tables()`
H A D	vega12_hwmgr.c	`1132 PP_ASSERT_WITH_CODE(table->count <= MAX_REGULAR_DPM_NUMBER, in vega12_find_highest_dpm_level() 1134 return MAX_REGULAR_DPM_NUMBER - 1); in vega12_find_highest_dpm_level()`
H A D	vega20_hwmgr.c	`1793 PP_ASSERT_WITH_CODE(table->count <= MAX_REGULAR_DPM_NUMBER, in vega20_find_highest_dpm_level() 1795 return MAX_REGULAR_DPM_NUMBER - 1); in vega20_find_highest_dpm_level()`
H A D	vega10_hwmgr.c	`1793 while (i < MAX_REGULAR_DPM_NUMBER) { in vega10_populate_vddc_soc_levels() 3584 if (table->count <= MAX_REGULAR_DPM_NUMBER) { in vega10_find_highest_dpm_level() 3591 return MAX_REGULAR_DPM_NUMBER - 1; in vega10_find_highest_dpm_level()`
/kernel/linux/linux-5.10/drivers/gpu/drm/radeon/
H A D	ci_dpm.h	`60 #define MAX_REGULAR_DPM_NUMBER 8 macro 65 struct ci_dpm_level dpm_levels[MAX_REGULAR_DPM_NUMBER];`
H A D	ci_dpm.c	`3366 for (i = 0; i < MAX_REGULAR_DPM_NUMBER; i++) in ci_reset_single_dpm_table()`
/kernel/linux/linux-6.6/drivers/gpu/drm/radeon/
H A D	ci_dpm.h	`60 #define MAX_REGULAR_DPM_NUMBER 8 macro 65 struct ci_dpm_level dpm_levels[MAX_REGULAR_DPM_NUMBER];`
H A D	ci_dpm.c	`3342 for (i = 0; i < MAX_REGULAR_DPM_NUMBER; i++) in ci_reset_single_dpm_table()`

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