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Searched refs:MASTER_COMM_CMD_REG (Results 1 - 10 of 10) sorted by relevance

/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_dmcu.h41 SR(MASTER_COMM_CMD_REG), \
59 SR(MASTER_COMM_CMD_REG), \
76 SR(MASTER_COMM_CMD_REG), \
112 DMCU_SF(MASTER_COMM_CMD_REG, \
139 DMCU_SF(MASTER_COMM_CMD_REG, \
157 DMCU_SF(MASTER_COMM_CMD_REG, \
212 uint32_t MASTER_COMM_CMD_REG; member
H A Ddce_dmcu.c141 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, in dce_dmcu_set_psr_enable()
144 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, in dce_dmcu_set_psr_enable()
267 REG_UPDATE(MASTER_COMM_CMD_REG, in dce_dmcu_setup_psr()
314 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, PSR_SET_WAITLOOP); in dce_psr_wait_loop()
366 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, in dcn10_dmcu_enable_fractional_pwm()
421 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, in dcn10_dmcu_init()
504 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, in dcn10_dmcu_load_iram()
563 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, in dcn10_dmcu_set_psr_enable()
566 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, in dcn10_dmcu_set_psr_enable()
707 REG_UPDATE(MASTER_COMM_CMD_REG, in dcn10_dmcu_setup_psr()
[all...]
H A Ddce_abm.h34 SR(MASTER_COMM_CMD_REG), \
108 ABM_SF(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, mask_sh), \
109 ABM_SF(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE1, mask_sh), \
110 ABM_SF(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE2, mask_sh)
222 uint32_t MASTER_COMM_CMD_REG; member
H A Ddce_abm.c73 REG_UPDATE_2(MASTER_COMM_CMD_REG, in dce_abm_set_pipe()
118 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, MCP_BL_SET); in dmcu_set_backlight_level()
210 REG_UPDATE_2(MASTER_COMM_CMD_REG, in dce_abm_set_level()
H A Ddce_link_encoder.h151 uint32_t MASTER_COMM_CMD_REG; member
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_dmcu.h41 SR(MASTER_COMM_CMD_REG), \
63 SR(MASTER_COMM_CMD_REG), \
80 SR(MASTER_COMM_CMD_REG), \
116 DMCU_SF(MASTER_COMM_CMD_REG, \
144 DMCU_SF(MASTER_COMM_CMD_REG, \
162 DMCU_SF(MASTER_COMM_CMD_REG, \
218 uint32_t MASTER_COMM_CMD_REG; member
H A Ddce_dmcu.c145 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, in dce_dmcu_set_psr_enable()
148 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, in dce_dmcu_set_psr_enable()
271 REG_UPDATE(MASTER_COMM_CMD_REG, in dce_dmcu_setup_psr()
318 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, PSR_SET_WAITLOOP); in dce_psr_wait_loop()
369 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, in dcn10_dmcu_enable_fractional_pwm()
424 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, in dcn10_dmcu_init()
507 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, in dcn10_dmcu_load_iram()
566 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, in dcn10_dmcu_set_psr_enable()
569 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, in dcn10_dmcu_set_psr_enable()
711 REG_UPDATE(MASTER_COMM_CMD_REG, in dcn10_dmcu_setup_psr()
[all...]
H A Ddce_abm.c73 REG_UPDATE_2(MASTER_COMM_CMD_REG, in dce_abm_set_pipe()
118 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, MCP_BL_SET); in dmcu_set_backlight_level()
210 REG_UPDATE_2(MASTER_COMM_CMD_REG, in dce_abm_set_level()
H A Ddce_abm.h34 SR(MASTER_COMM_CMD_REG), \
151 ABM_SF(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, mask_sh), \
152 ABM_SF(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE1, mask_sh), \
153 ABM_SF(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE2, mask_sh)
320 uint32_t MASTER_COMM_CMD_REG; member
H A Ddce_link_encoder.h151 uint32_t MASTER_COMM_CMD_REG; member

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