Searched refs:LINE1_IRQ (Results 1 - 2 of 2) sorted by relevance
/kernel/linux/linux-5.10/drivers/gpu/drm/imx/dcss/ |
H A D | dcss-dtg.c | 68 #define LINE1_IRQ BIT(1) macro 133 dcss_update(0, LINE0_IRQ | LINE1_IRQ, in dcss_dtg_irq_config() 360 u32 mask = en ? LINE1_IRQ : 0; in dcss_dtg_vblank_irq_enable() 364 dcss_writel(status & LINE1_IRQ, in dcss_dtg_vblank_irq_enable() 368 dcss_update(mask, LINE1_IRQ, dtg->base_reg + DCSS_DTG_INT_MASK); in dcss_dtg_vblank_irq_enable() 402 dcss_update(LINE1_IRQ, LINE1_IRQ, dtg->base_reg + DCSS_DTG_INT_CONTROL); in dcss_dtg_vblank_irq_clear() 407 return !!(dcss_readl(dtg->base_reg + DCSS_DTG_INT_STATUS) & LINE1_IRQ); in dcss_dtg_vblank_irq_valid()
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/kernel/linux/linux-6.6/drivers/gpu/drm/imx/dcss/ |
H A D | dcss-dtg.c | 68 #define LINE1_IRQ BIT(1) macro 133 dcss_update(0, LINE0_IRQ | LINE1_IRQ, in dcss_dtg_irq_config() 360 u32 mask = en ? LINE1_IRQ : 0; in dcss_dtg_vblank_irq_enable() 364 dcss_writel(status & LINE1_IRQ, in dcss_dtg_vblank_irq_enable() 368 dcss_update(mask, LINE1_IRQ, dtg->base_reg + DCSS_DTG_INT_MASK); in dcss_dtg_vblank_irq_enable() 402 dcss_update(LINE1_IRQ, LINE1_IRQ, dtg->base_reg + DCSS_DTG_INT_CONTROL); in dcss_dtg_vblank_irq_clear() 407 return !!(dcss_readl(dtg->base_reg + DCSS_DTG_INT_STATUS) & LINE1_IRQ); in dcss_dtg_vblank_irq_valid()
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