Searched refs:LINE0_IRQ (Results 1 - 2 of 2) sorted by relevance
/kernel/linux/linux-5.10/drivers/gpu/drm/imx/dcss/ |
H A D | dcss-dtg.c | 67 #define LINE0_IRQ BIT(0) macro 114 if (!(status & LINE0_IRQ)) in dcss_dtg_irq_handler() 119 dcss_writel(status & LINE0_IRQ, dtg->base_reg + DCSS_DTG_INT_CONTROL); in dcss_dtg_irq_handler() 133 dcss_update(0, LINE0_IRQ | LINE1_IRQ, in dcss_dtg_irq_config() 374 u32 mask = en ? LINE0_IRQ : 0; in dcss_dtg_ctxld_kick_irq_enable() 380 dcss_writel(status & LINE0_IRQ, in dcss_dtg_ctxld_kick_irq_enable() 384 dcss_update(mask, LINE0_IRQ, in dcss_dtg_ctxld_kick_irq_enable() 397 dcss_update(mask, LINE0_IRQ, dtg->base_reg + DCSS_DTG_INT_MASK); in dcss_dtg_ctxld_kick_irq_enable()
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/kernel/linux/linux-6.6/drivers/gpu/drm/imx/dcss/ |
H A D | dcss-dtg.c | 67 #define LINE0_IRQ BIT(0) macro 114 if (!(status & LINE0_IRQ)) in dcss_dtg_irq_handler() 119 dcss_writel(status & LINE0_IRQ, dtg->base_reg + DCSS_DTG_INT_CONTROL); in dcss_dtg_irq_handler() 133 dcss_update(0, LINE0_IRQ | LINE1_IRQ, in dcss_dtg_irq_config() 374 u32 mask = en ? LINE0_IRQ : 0; in dcss_dtg_ctxld_kick_irq_enable() 380 dcss_writel(status & LINE0_IRQ, in dcss_dtg_ctxld_kick_irq_enable() 384 dcss_update(mask, LINE0_IRQ, in dcss_dtg_ctxld_kick_irq_enable() 397 dcss_update(mask, LINE0_IRQ, dtg->base_reg + DCSS_DTG_INT_MASK); in dcss_dtg_ctxld_kick_irq_enable()
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