JZ4760_CLK_PLL1 (reference) in projects: kernel

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/kernel/linux/linux-6.6/drivers/clk/ingenic/
H A D	jz4760-cgu.c	`116 [JZ4760_CLK_PLL1] = { 216 .parents = { JZ4760_CLK_PLL0_HALF, JZ4760_CLK_PLL1, }, 223 .parents = { JZ4760_CLK_PLL0_HALF, JZ4760_CLK_PLL1, }, 230 .parents = { JZ4760_CLK_PLL0_HALF, JZ4760_CLK_PLL1, }, 248 .parents = { JZ4760_CLK_PLL0_HALF, JZ4760_CLK_PLL1, }, 259 JZ4760_CLK_PLL0_HALF, JZ4760_CLK_PLL1 }, 267 JZ4760_CLK_PLL0_HALF, JZ4760_CLK_PLL1 }, 274 JZ4760_CLK_PLL0_HALF, JZ4760_CLK_PLL1 },`
/kernel/linux/linux-6.6/include/dt-bindings/clock/
H A D	ingenic,jz4760-cgu.h	`13 #define JZ4760_CLK_PLL1 4 macro`
/kernel/linux/linux-6.6/scripts/dtc/include-prefixes/dt-bindings/clock/
H A D	ingenic,jz4760-cgu.h	`13 #define JZ4760_CLK_PLL1 4 macro`