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Searched refs:IP5_27_24 (Results 1 - 19 of 19) sorted by relevance

/kernel/linux/linux-5.10/drivers/pinctrl/renesas/
H A Dpfc-r8a77970.c118 #define GPSR3_6 F_(VI1_DATA2, IP5_27_24)
199 #define IP5_27_24 FM(VI1_DATA2) FM(CANFD0_TX_B) F_(0, 0) FM(D5) FM(MMC_D0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) macro
274 FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
583 PINMUX_IPSR_GPSR(IP5_27_24, VI1_DATA2),
584 PINMUX_IPSR_MSEL(IP5_27_24, CANFD0_TX_B, SEL_CANFD0_1),
585 PINMUX_IPSR_GPSR(IP5_27_24, D5),
586 PINMUX_IPSR_GPSR(IP5_27_24, MMC_D0),
2392 IP5_27_24
H A Dpfc-r8a77990.c84 #define GPSR0_1 F_(D1, IP5_27_24)
262 #define IP5_27_24 FM(D1) FM(MSIOF3_SYNC_A) FM(SCK3_A) FM(VI4_DATA23) FM(VI5_CLKENB_A) FM(DU_DB7) FM(RTS4_N_C) F_(0, 0) FM(LCDOUT7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) macro
401 FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
837 PINMUX_IPSR_GPSR(IP5_27_24, D1),
838 PINMUX_IPSR_MSEL(IP5_27_24, MSIOF3_SYNC_A, SEL_MSIOF3_0),
839 PINMUX_IPSR_MSEL(IP5_27_24, SCK3_A, SEL_SCIF3_0),
840 PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA23),
841 PINMUX_IPSR_MSEL(IP5_27_24, VI5_CLKENB_A, SEL_VIN5_0),
842 PINMUX_IPSR_GPSR(IP5_27_24, DU_DB
[all...]
H A Dpfc-r8a77980.c132 #define GPSR3_6 F_(VI1_DATA2, IP5_27_24)
232 #define IP5_27_24 FM(VI1_DATA2) FM(CANFD0_TX_B) F_(0, 0) FM(D5) FM(MMC_DS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) macro
325 FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
661 PINMUX_IPSR_GPSR(IP5_27_24, VI1_DATA2),
662 PINMUX_IPSR_MSEL(IP5_27_24, CANFD0_TX_B, SEL_CANFD0_1),
663 PINMUX_IPSR_GPSR(IP5_27_24, D5),
664 PINMUX_IPSR_GPSR(IP5_27_24, MMC_DS),
2814 IP5_27_24
H A Dpfc-r8a7779.c987 PINMUX_IPSR_GPSR(IP5_27_24, DU1_CDE),
988 PINMUX_IPSR_GPSR(IP5_27_24, VI2_DATA7_VI2_B7),
989 PINMUX_IPSR_MSEL(IP5_27_24, RX3_B_IRDA_RX_B, SEL_SCIF3_1),
990 PINMUX_IPSR_GPSR(IP5_27_24, SD3_WP),
991 PINMUX_IPSR_MSEL(IP5_27_24, HSPI_RX1, SEL_HSPI1_0),
992 PINMUX_IPSR_GPSR(IP5_27_24, VI1_FIELD),
993 PINMUX_IPSR_GPSR(IP5_27_24, VI3_FIELD),
994 PINMUX_IPSR_GPSR(IP5_27_24, AUDIO_CLKOUT),
995 PINMUX_IPSR_MSEL(IP5_27_24, RX2_D, SEL_SCIF2_3),
996 PINMUX_IPSR_MSEL(IP5_27_24, GPS_CLK_
[all...]
H A Dpfc-r8a77995.c102 #define GPSR2_9 F_(VI4_DATA8, IP5_27_24)
247 #define IP5_27_24 FM(VI4_DATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) macro
364 FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
700 PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA8),
2673 IP5_27_24
H A Dpfc-r8a77951.c94 #define GPSR0_3 F_(D3, IP5_27_24)
303 #define IP5_27_24 FM(D3) F_(0, 0) FM(MSIOF3_TXD_A) F_(0, 0) FM(VI4_DATA19) FM(VI5_DATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) macro
461 FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
944 PINMUX_IPSR_GPSR(IP5_27_24, D3),
945 PINMUX_IPSR_MSEL(IP5_27_24, MSIOF3_TXD_A, SEL_MSIOF3_0),
946 PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA19),
947 PINMUX_IPSR_GPSR(IP5_27_24, VI5_DATA3),
5441 IP5_27_24
H A Dpfc-r8a77965.c99 #define GPSR0_3 F_(D3, IP5_27_24)
308 #define IP5_27_24 FM(D3) F_(0, 0) FM(MSIOF3_TXD_A) F_(0, 0) FM(VI4_DATA19) FM(VI5_DATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) macro
466 FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
950 PINMUX_IPSR_GPSR(IP5_27_24, D3),
951 PINMUX_IPSR_MSEL(IP5_27_24, MSIOF3_TXD_A, SEL_MSIOF3_0),
952 PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA19),
953 PINMUX_IPSR_GPSR(IP5_27_24, VI5_DATA3),
5647 IP5_27_24
H A Dpfc-r8a7796.c99 #define GPSR0_3 F_(D3, IP5_27_24)
308 #define IP5_27_24 FM(D3) F_(0, 0) FM(MSIOF3_TXD_A) F_(0, 0) FM(VI4_DATA19) FM(VI5_DATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) macro
466 FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
948 PINMUX_IPSR_GPSR(IP5_27_24, D3),
949 PINMUX_IPSR_MSEL(IP5_27_24, MSIOF3_TXD_A, SEL_MSIOF3_0),
950 PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA19),
951 PINMUX_IPSR_GPSR(IP5_27_24, VI5_DATA3),
5394 IP5_27_24
H A Dpfc-r8a77950.c94 #define GPSR0_3 F_(D3, IP5_27_24)
302 #define IP5_27_24 FM(D3) F_(0, 0) FM(MSIOF3_TXD_A) F_(0, 0) FM(VI4_DATA19) FM(VI5_DATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) macro
451 FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
937 PINMUX_IPSR_GPSR(IP5_27_24, D3),
938 PINMUX_IPSR_MSEL(IP5_27_24, MSIOF3_TXD_A, SEL_MSIOF3_0),
939 PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA19),
940 PINMUX_IPSR_GPSR(IP5_27_24, VI5_DATA3),
5080 IP5_27_24
H A Dpfc-r8a77470.c718 PINMUX_IPSR_GPSR(IP5_27_24, DU0_DG5),
719 PINMUX_IPSR_MSEL(IP5_27_24, HTX0_A, SEL_HSCIF0_0),
720 PINMUX_IPSR_GPSR(IP5_27_24, PWM5_B),
721 PINMUX_IPSR_GPSR(IP5_27_24, A13),
2895 /* IP5_27_24 [4] */
/kernel/linux/linux-6.6/drivers/pinctrl/renesas/
H A Dpfc-r8a77970.c129 #define GPSR3_6 F_(VI1_DATA2, IP5_27_24)
210 #define IP5_27_24 FM(VI1_DATA2) FM(CANFD0_TX_B) F_(0, 0) FM(D5) FM(MMC_D0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) macro
284 FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
592 PINMUX_IPSR_GPSR(IP5_27_24, VI1_DATA2),
593 PINMUX_IPSR_MSEL(IP5_27_24, CANFD0_TX_B, SEL_CANFD0_1),
594 PINMUX_IPSR_GPSR(IP5_27_24, D5),
595 PINMUX_IPSR_GPSR(IP5_27_24, MMC_D0),
2284 IP5_27_24
H A Dpfc-r8a77990.c84 #define GPSR0_1 F_(D1, IP5_27_24)
262 #define IP5_27_24 FM(D1) FM(MSIOF3_SYNC_A) FM(SCK3_A) FM(VI4_DATA23) FM(VI5_CLKENB_A) FM(DU_DB7) FM(RTS4_N_C) F_(0, 0) FM(LCDOUT7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) macro
401 FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
838 PINMUX_IPSR_GPSR(IP5_27_24, D1),
839 PINMUX_IPSR_MSEL(IP5_27_24, MSIOF3_SYNC_A, SEL_MSIOF3_0),
840 PINMUX_IPSR_MSEL(IP5_27_24, SCK3_A, SEL_SCIF3_0),
841 PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA23),
842 PINMUX_IPSR_MSEL(IP5_27_24, VI5_CLKENB_A, SEL_VIN5_0),
843 PINMUX_IPSR_GPSR(IP5_27_24, DU_DB
[all...]
H A Dpfc-r8a77980.c144 #define GPSR3_6 F_(VI1_DATA2, IP5_27_24)
244 #define IP5_27_24 FM(VI1_DATA2) FM(CANFD0_TX_B) F_(0, 0) FM(D5) FM(MMC_DS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) macro
334 FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
670 PINMUX_IPSR_GPSR(IP5_27_24, VI1_DATA2),
671 PINMUX_IPSR_MSEL(IP5_27_24, CANFD0_TX_B, SEL_CANFD0_1),
672 PINMUX_IPSR_GPSR(IP5_27_24, D5),
673 PINMUX_IPSR_GPSR(IP5_27_24, MMC_DS),
2738 IP5_27_24
H A Dpfc-r8a7779.c1050 PINMUX_IPSR_GPSR(IP5_27_24, DU1_CDE),
1051 PINMUX_IPSR_GPSR(IP5_27_24, VI2_DATA7_VI2_B7),
1052 PINMUX_IPSR_MSEL(IP5_27_24, RX3_B_IRDA_RX_B, SEL_SCIF3_1),
1053 PINMUX_IPSR_GPSR(IP5_27_24, SD3_WP),
1054 PINMUX_IPSR_MSEL(IP5_27_24, HSPI_RX1, SEL_HSPI1_0),
1055 PINMUX_IPSR_GPSR(IP5_27_24, VI1_FIELD),
1056 PINMUX_IPSR_GPSR(IP5_27_24, VI3_FIELD),
1057 PINMUX_IPSR_GPSR(IP5_27_24, AUDIO_CLKOUT),
1058 PINMUX_IPSR_MSEL(IP5_27_24, RX2_D, SEL_SCIF2_3),
1059 PINMUX_IPSR_MSEL(IP5_27_24, GPS_CLK_
[all...]
H A Dpfc-r8a77995.c113 #define GPSR2_9 F_(VI4_DATA8, IP5_27_24)
258 #define IP5_27_24 FM(VI4_DATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) macro
375 FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
711 PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA8),
2725 IP5_27_24
H A Dpfc-r8a77951.c93 #define GPSR0_3 F_(D3, IP5_27_24)
302 #define IP5_27_24 FM(D3) F_(0, 0) FM(MSIOF3_TXD_A) F_(0, 0) FM(VI4_DATA19) FM(VI5_DATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) macro
460 FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
943 PINMUX_IPSR_GPSR(IP5_27_24, D3),
944 PINMUX_IPSR_MSEL(IP5_27_24, MSIOF3_TXD_A, SEL_MSIOF3_0),
945 PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA19),
946 PINMUX_IPSR_GPSR(IP5_27_24, VI5_DATA3),
5399 IP5_27_24
H A Dpfc-r8a77965.c98 #define GPSR0_3 F_(D3, IP5_27_24)
307 #define IP5_27_24 FM(D3) F_(0, 0) FM(MSIOF3_TXD_A) F_(0, 0) FM(VI4_DATA19) FM(VI5_DATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) macro
465 FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
949 PINMUX_IPSR_GPSR(IP5_27_24, D3),
950 PINMUX_IPSR_MSEL(IP5_27_24, MSIOF3_TXD_A, SEL_MSIOF3_0),
951 PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA19),
952 PINMUX_IPSR_GPSR(IP5_27_24, VI5_DATA3),
5595 IP5_27_24
H A Dpfc-r8a7796.c98 #define GPSR0_3 F_(D3, IP5_27_24)
307 #define IP5_27_24 FM(D3) F_(0, 0) FM(MSIOF3_TXD_A) F_(0, 0) FM(VI4_DATA19) FM(VI5_DATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) macro
465 FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
947 PINMUX_IPSR_GPSR(IP5_27_24, D3),
948 PINMUX_IPSR_MSEL(IP5_27_24, MSIOF3_TXD_A, SEL_MSIOF3_0),
949 PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA19),
950 PINMUX_IPSR_GPSR(IP5_27_24, VI5_DATA3),
5354 IP5_27_24
H A Dpfc-r8a77470.c728 PINMUX_IPSR_GPSR(IP5_27_24, DU0_DG5),
729 PINMUX_IPSR_MSEL(IP5_27_24, HTX0_A, SEL_HSCIF0_0),
730 PINMUX_IPSR_GPSR(IP5_27_24, PWM5_B),
731 PINMUX_IPSR_GPSR(IP5_27_24, A13),
2810 /* IP5_27_24 [4] */

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