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Searched refs:IP4_3_0 (Results 1 - 17 of 17) sorted by relevance

/kernel/linux/linux-5.10/drivers/pinctrl/renesas/
H A Dpfc-r8a77970.c96 #define GPSR2_9 F_(VI0_DATA5, IP4_3_0)
185 #define IP4_3_0 FM(VI0_DATA5) FM(HCTS1_N) FM(TX1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) macro
268 FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
520 PINMUX_IPSR_GPSR(IP4_3_0, VI0_DATA5),
521 PINMUX_IPSR_GPSR(IP4_3_0, HCTS1_N),
522 PINMUX_IPSR_MSEL(IP4_3_0, TX1_A, SEL_SCIF1_0),
2388 IP4_3_0 ))
H A Dpfc-r8a77990.c101 #define GPSR1_9 F_(A9, IP4_3_0)
248 #define IP4_3_0 FM(A9) FM(TX5_A) FM(IRQ3) FM(VI4_DATA16) FM(VI5_VSYNC_N_A) FM(DU_DG7) F_(0, 0) F_(0, 0) FM(LCDOUT15) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) macro
395 FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
730 PINMUX_IPSR_GPSR(IP4_3_0, A9),
731 PINMUX_IPSR_GPSR(IP4_3_0, TX5_A),
732 PINMUX_IPSR_GPSR(IP4_3_0, IRQ3),
733 PINMUX_IPSR_GPSR(IP4_3_0, VI4_DATA16),
734 PINMUX_IPSR_MSEL(IP4_3_0, VI5_VSYNC_N_A, SEL_VIN5_0),
735 PINMUX_IPSR_GPSR(IP4_3_0, DU_DG
[all...]
H A Dpfc-r8a77980.c110 #define GPSR2_9 F_(VI0_DATA5, IP4_3_0)
218 #define IP4_3_0 FM(VI0_DATA5) FM(HCTS1_N) FM(TX1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) macro
319 FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
602 PINMUX_IPSR_GPSR(IP4_3_0, VI0_DATA5),
603 PINMUX_IPSR_GPSR(IP4_3_0, HCTS1_N),
604 PINMUX_IPSR_MSEL(IP4_3_0, TX1_A, SEL_SCIF1_0),
2810 IP4_3_0 ))
H A Dpfc-r8a77995.c52 #define GPSR1_25 F_(DU_HSYNC, IP4_3_0)
233 #define IP4_3_0 FM(DU_HSYNC) FM(QSTH_QHS) FM(IRQ3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) macro
358 FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
651 PINMUX_IPSR_GPSR(IP4_3_0, DU_HSYNC),
652 PINMUX_IPSR_GPSR(IP4_3_0, QSTH_QHS),
653 PINMUX_IPSR_MSEL(IP4_3_0, IRQ3_A, SEL_IRQ_3_0),
2669 IP4_3_0 ))
H A Dpfc-r8a77951.c111 #define GPSR1_17 F_(A17, IP4_3_0)
289 #define IP4_3_0 FM(A17) FM(LCDOUT9) F_(0, 0) F_(0, 0) FM(VI4_VSYNC_N) F_(0, 0) FM(DU_DG1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) macro
455 FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
859 PINMUX_IPSR_GPSR(IP4_3_0, A17),
860 PINMUX_IPSR_GPSR(IP4_3_0, LCDOUT9),
861 PINMUX_IPSR_GPSR(IP4_3_0, VI4_VSYNC_N),
862 PINMUX_IPSR_GPSR(IP4_3_0, DU_DG1),
5437 IP4_3_0 ))
H A Dpfc-r8a77965.c116 #define GPSR1_17 F_(A17, IP4_3_0)
294 #define IP4_3_0 FM(A17) FM(LCDOUT9) F_(0, 0) F_(0, 0) FM(VI4_VSYNC_N) F_(0, 0) FM(DU_DG1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) macro
460 FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
865 PINMUX_IPSR_GPSR(IP4_3_0, A17),
866 PINMUX_IPSR_GPSR(IP4_3_0, LCDOUT9),
867 PINMUX_IPSR_GPSR(IP4_3_0, VI4_VSYNC_N),
868 PINMUX_IPSR_GPSR(IP4_3_0, DU_DG1),
5643 IP4_3_0 ))
H A Dpfc-r8a7796.c116 #define GPSR1_17 F_(A17, IP4_3_0)
294 #define IP4_3_0 FM(A17) FM(LCDOUT9) F_(0, 0) F_(0, 0) FM(VI4_VSYNC_N) F_(0, 0) FM(DU_DG1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) macro
460 FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
863 PINMUX_IPSR_GPSR(IP4_3_0, A17),
864 PINMUX_IPSR_GPSR(IP4_3_0, LCDOUT9),
865 PINMUX_IPSR_GPSR(IP4_3_0, VI4_VSYNC_N),
866 PINMUX_IPSR_GPSR(IP4_3_0, DU_DG1),
5390 IP4_3_0 ))
H A Dpfc-r8a77950.c110 #define GPSR1_17 F_(A17, IP4_3_0)
288 #define IP4_3_0 FM(A17) FM(LCDOUT9) F_(0, 0) F_(0, 0) FM(VI4_VSYNC_N) F_(0, 0) FM(DU_DG1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) macro
445 FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
852 PINMUX_IPSR_GPSR(IP4_3_0, A17),
853 PINMUX_IPSR_GPSR(IP4_3_0, LCDOUT9),
854 PINMUX_IPSR_GPSR(IP4_3_0, VI4_VSYNC_N),
855 PINMUX_IPSR_GPSR(IP4_3_0, DU_DG1),
5076 IP4_3_0 ))
H A Dpfc-r8a77470.c663 PINMUX_IPSR_GPSR(IP4_3_0, EX_WAIT0),
664 PINMUX_IPSR_MSEL(IP4_3_0, CAN_CLK_B, SEL_CANCLK_1),
665 PINMUX_IPSR_MSEL(IP4_3_0, SCIF_CLK_A, SEL_SCIFCLK_0),
2885 /* IP4_3_0 [4] */
/kernel/linux/linux-6.6/drivers/pinctrl/renesas/
H A Dpfc-r8a77970.c107 #define GPSR2_9 F_(VI0_DATA5, IP4_3_0)
196 #define IP4_3_0 FM(VI0_DATA5) FM(HCTS1_N) FM(TX1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) macro
278 FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
529 PINMUX_IPSR_GPSR(IP4_3_0, VI0_DATA5),
530 PINMUX_IPSR_GPSR(IP4_3_0, HCTS1_N),
531 PINMUX_IPSR_MSEL(IP4_3_0, TX1_A, SEL_SCIF1_0),
2280 IP4_3_0 ))
H A Dpfc-r8a77990.c101 #define GPSR1_9 F_(A9, IP4_3_0)
248 #define IP4_3_0 FM(A9) FM(TX5_A) FM(IRQ3) FM(VI4_DATA16) FM(VI5_VSYNC_N_A) FM(DU_DG7) F_(0, 0) F_(0, 0) FM(LCDOUT15) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) macro
395 FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
731 PINMUX_IPSR_GPSR(IP4_3_0, A9),
732 PINMUX_IPSR_GPSR(IP4_3_0, TX5_A),
733 PINMUX_IPSR_GPSR(IP4_3_0, IRQ3),
734 PINMUX_IPSR_GPSR(IP4_3_0, VI4_DATA16),
735 PINMUX_IPSR_MSEL(IP4_3_0, VI5_VSYNC_N_A, SEL_VIN5_0),
736 PINMUX_IPSR_GPSR(IP4_3_0, DU_DG
[all...]
H A Dpfc-r8a77995.c63 #define GPSR1_25 F_(DU_HSYNC, IP4_3_0)
244 #define IP4_3_0 FM(DU_HSYNC) FM(QSTH_QHS) FM(IRQ3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) macro
369 FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
662 PINMUX_IPSR_GPSR(IP4_3_0, DU_HSYNC),
663 PINMUX_IPSR_GPSR(IP4_3_0, QSTH_QHS),
664 PINMUX_IPSR_MSEL(IP4_3_0, IRQ3_A, SEL_IRQ_3_0),
2721 IP4_3_0 ))
H A Dpfc-r8a77980.c122 #define GPSR2_9 F_(VI0_DATA5, IP4_3_0)
230 #define IP4_3_0 FM(VI0_DATA5) FM(HCTS1_N) FM(TX1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) macro
328 FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
611 PINMUX_IPSR_GPSR(IP4_3_0, VI0_DATA5),
612 PINMUX_IPSR_GPSR(IP4_3_0, HCTS1_N),
613 PINMUX_IPSR_MSEL(IP4_3_0, TX1_A, SEL_SCIF1_0),
2734 IP4_3_0 ))
H A Dpfc-r8a77951.c110 #define GPSR1_17 F_(A17, IP4_3_0)
288 #define IP4_3_0 FM(A17) FM(LCDOUT9) F_(0, 0) F_(0, 0) FM(VI4_VSYNC_N) F_(0, 0) FM(DU_DG1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) macro
454 FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
858 PINMUX_IPSR_GPSR(IP4_3_0, A17),
859 PINMUX_IPSR_GPSR(IP4_3_0, LCDOUT9),
860 PINMUX_IPSR_GPSR(IP4_3_0, VI4_VSYNC_N),
861 PINMUX_IPSR_GPSR(IP4_3_0, DU_DG1),
5395 IP4_3_0 ))
H A Dpfc-r8a77965.c115 #define GPSR1_17 F_(A17, IP4_3_0)
293 #define IP4_3_0 FM(A17) FM(LCDOUT9) F_(0, 0) F_(0, 0) FM(VI4_VSYNC_N) F_(0, 0) FM(DU_DG1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) macro
459 FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
864 PINMUX_IPSR_GPSR(IP4_3_0, A17),
865 PINMUX_IPSR_GPSR(IP4_3_0, LCDOUT9),
866 PINMUX_IPSR_GPSR(IP4_3_0, VI4_VSYNC_N),
867 PINMUX_IPSR_GPSR(IP4_3_0, DU_DG1),
5591 IP4_3_0 ))
H A Dpfc-r8a7796.c115 #define GPSR1_17 F_(A17, IP4_3_0)
293 #define IP4_3_0 FM(A17) FM(LCDOUT9) F_(0, 0) F_(0, 0) FM(VI4_VSYNC_N) F_(0, 0) FM(DU_DG1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) macro
459 FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
862 PINMUX_IPSR_GPSR(IP4_3_0, A17),
863 PINMUX_IPSR_GPSR(IP4_3_0, LCDOUT9),
864 PINMUX_IPSR_GPSR(IP4_3_0, VI4_VSYNC_N),
865 PINMUX_IPSR_GPSR(IP4_3_0, DU_DG1),
5350 IP4_3_0 ))
H A Dpfc-r8a77470.c673 PINMUX_IPSR_GPSR(IP4_3_0, EX_WAIT0),
674 PINMUX_IPSR_MSEL(IP4_3_0, CAN_CLK_B, SEL_CANCLK_1),
675 PINMUX_IPSR_MSEL(IP4_3_0, SCIF_CLK_A, SEL_SCIFCLK_0),
2802 /* IP4_3_0 [4] */

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