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Searched refs:IP1_3_0 (Results 1 - 19 of 19) sorted by relevance

/kernel/linux/linux-5.10/drivers/pinctrl/renesas/
H A Dpfc-r8a77970.c48 #define GPSR0_8 F_(DU_DG4, IP1_3_0)
161 #define IP1_3_0 FM(DU_DG4) F_(0, 0) F_(0, 0) FM(A8) FM(FSO_CFE_0_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) macro
259 FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
418 PINMUX_IPSR_GPSR(IP1_3_0, DU_DG4),
419 PINMUX_IPSR_GPSR(IP1_3_0, A8),
420 PINMUX_IPSR_MSEL(IP1_3_0, FSO_CFE_0_N_A, SEL_RFSO_0),
2358 IP1_3_0 ))
H A Dpfc-r8a77980.c49 #define GPSR0_8 F_(DU_DG4, IP1_3_0)
194 #define IP1_3_0 FM(DU_DG4) FM(SCL5) F_(0, 0) FM(A8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) macro
310 FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
492 PINMUX_IPSR_GPSR(IP1_3_0, DU_DG4),
493 PINMUX_IPSR_GPSR(IP1_3_0, SCL5),
494 PINMUX_IPSR_GPSR(IP1_3_0, A8),
2780 IP1_3_0 ))
H A Dpfc-r8a77995.c76 #define GPSR1_1 F_(DU_DB1, IP1_3_0)
207 #define IP1_3_0 FM(DU_DB1) FM(LCDOUT1) FM(MSIOF3_RXD_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) macro
349 FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
554 PINMUX_IPSR_GPSR(IP1_3_0, DU_DB1),
555 PINMUX_IPSR_GPSR(IP1_3_0, LCDOUT1),
556 PINMUX_IPSR_MSEL(IP1_3_0, MSIOF3_RXD_B, SEL_MSIOF3_1),
2639 IP1_3_0 ))
H A Dpfc-r8a77990.c129 #define GPSR2_9 F_(QSPI1_IO2, IP1_3_0)
222 #define IP1_3_0 FM(QSPI1_IO2) FM(RIF2_D1_A) FM(HTX3_C) FM(VI4_DATA3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) macro
386 FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
585 PINMUX_IPSR_GPSR(IP1_3_0, QSPI1_IO2),
586 PINMUX_IPSR_MSEL(IP1_3_0, RIF2_D1_A, SEL_DRIF2_0),
587 PINMUX_IPSR_GPSR(IP1_3_0, HTX3_C),
588 PINMUX_IPSR_MSEL(IP1_3_0, VI4_DATA3_A, SEL_VIN4_0),
4786 IP1_3_0 ))
H A Dpfc-r8a77951.c143 #define GPSR2_2 F_(IRQ2, IP1_3_0)
263 #define IP1_3_0 FM(IRQ2) FM(QCPV_QDE) F_(0, 0) FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(VI4_DATA2_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SYNC_E) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) macro
446 FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
691 PINMUX_IPSR_GPSR(IP1_3_0, IRQ2),
692 PINMUX_IPSR_GPSR(IP1_3_0, QCPV_QDE),
693 PINMUX_IPSR_GPSR(IP1_3_0, DU_EXODDF_DU_ODDF_DISP_CDE),
694 PINMUX_IPSR_MSEL(IP1_3_0, VI4_DATA2_B, SEL_VIN4_1),
695 PINMUX_IPSR_MSEL(IP1_3_0, PWM3_B, SEL_PWM3_1),
696 PINMUX_IPSR_MSEL(IP1_3_0, MSIOF3_SYNC_
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H A Dpfc-r8a77965.c148 #define GPSR2_2 F_(IRQ2, IP1_3_0)
268 #define IP1_3_0 FM(IRQ2) FM(QCPV_QDE) F_(0, 0) FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(VI4_DATA2_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SYNC_E) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) macro
451 FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
697 PINMUX_IPSR_GPSR(IP1_3_0, IRQ2),
698 PINMUX_IPSR_GPSR(IP1_3_0, QCPV_QDE),
699 PINMUX_IPSR_GPSR(IP1_3_0, DU_EXODDF_DU_ODDF_DISP_CDE),
700 PINMUX_IPSR_MSEL(IP1_3_0, VI4_DATA2_B, SEL_VIN4_1),
701 PINMUX_IPSR_MSEL(IP1_3_0, PWM3_B, SEL_PWM3_1),
702 PINMUX_IPSR_MSEL(IP1_3_0, MSIOF3_SYNC_
[all...]
H A Dpfc-r8a7796.c148 #define GPSR2_2 F_(IRQ2, IP1_3_0)
268 #define IP1_3_0 FM(IRQ2) FM(QCPV_QDE) F_(0, 0) FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(VI4_DATA2_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SYNC_E) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) macro
451 FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
696 PINMUX_IPSR_GPSR(IP1_3_0, IRQ2),
697 PINMUX_IPSR_GPSR(IP1_3_0, QCPV_QDE),
698 PINMUX_IPSR_GPSR(IP1_3_0, DU_EXODDF_DU_ODDF_DISP_CDE),
699 PINMUX_IPSR_MSEL(IP1_3_0, VI4_DATA2_B, SEL_VIN4_1),
700 PINMUX_IPSR_MSEL(IP1_3_0, PWM3_B, SEL_PWM3_1),
701 PINMUX_IPSR_MSEL(IP1_3_0, MSIOF3_SYNC_
[all...]
H A Dpfc-r8a77950.c142 #define GPSR2_2 F_(IRQ2, IP1_3_0)
262 #define IP1_3_0 FM(IRQ2) FM(QCPV_QDE) F_(0, 0) FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(VI4_DATA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) macro
436 FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
683 PINMUX_IPSR_GPSR(IP1_3_0, IRQ2),
684 PINMUX_IPSR_GPSR(IP1_3_0, QCPV_QDE),
685 PINMUX_IPSR_GPSR(IP1_3_0, DU_EXODDF_DU_ODDF_DISP_CDE),
686 PINMUX_IPSR_MSEL(IP1_3_0, VI4_DATA2_B, SEL_VIN4_1),
687 PINMUX_IPSR_MSEL(IP1_3_0, PWM3_B, SEL_PWM3_1),
5046 IP1_3_0 ))
[all...]
H A Dpfc-r8a7790.c857 PINMUX_IPSR_GPSR(IP1_3_0, D9),
858 PINMUX_IPSR_MSEL(IP1_3_0, SCIFA1_RXD_C, SEL_SCIFA1_2),
859 PINMUX_IPSR_GPSR(IP1_3_0, AVB_TXD1),
860 PINMUX_IPSR_MSEL(IP1_3_0, VI0_G1, SEL_VI0_0),
861 PINMUX_IPSR_MSEL(IP1_3_0, VI0_G1_B, SEL_VI0_1),
862 PINMUX_IPSR_MSEL(IP1_3_0, VI2_DATA1_VI2_B1, SEL_VI2_0),
5157 /* IP1_3_0 [4] */
H A Dpfc-r8a77470.c568 PINMUX_IPSR_GPSR(IP1_3_0, MMC0_D4),
569 PINMUX_IPSR_GPSR(IP1_3_0, SD1_CD),
2800 /* IP1_3_0 [4] */
/kernel/linux/linux-6.6/drivers/pinctrl/renesas/
H A Dpfc-r8a77970.c59 #define GPSR0_8 F_(DU_DG4, IP1_3_0)
172 #define IP1_3_0 FM(DU_DG4) F_(0, 0) F_(0, 0) FM(A8) FM(FSO_CFE_0_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) macro
269 FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
427 PINMUX_IPSR_GPSR(IP1_3_0, DU_DG4),
428 PINMUX_IPSR_GPSR(IP1_3_0, A8),
429 PINMUX_IPSR_MSEL(IP1_3_0, FSO_CFE_0_N_A, SEL_RFSO_0),
2250 IP1_3_0 ))
H A Dpfc-r8a77995.c87 #define GPSR1_1 F_(DU_DB1, IP1_3_0)
218 #define IP1_3_0 FM(DU_DB1) FM(LCDOUT1) FM(MSIOF3_RXD_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) macro
360 FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
565 PINMUX_IPSR_GPSR(IP1_3_0, DU_DB1),
566 PINMUX_IPSR_GPSR(IP1_3_0, LCDOUT1),
567 PINMUX_IPSR_MSEL(IP1_3_0, MSIOF3_RXD_B, SEL_MSIOF3_1),
2691 IP1_3_0 ))
H A Dpfc-r8a77980.c61 #define GPSR0_8 F_(DU_DG4, IP1_3_0)
206 #define IP1_3_0 FM(DU_DG4) FM(SCL5) F_(0, 0) FM(A8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) macro
319 FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
501 PINMUX_IPSR_GPSR(IP1_3_0, DU_DG4),
502 PINMUX_IPSR_GPSR(IP1_3_0, SCL5),
503 PINMUX_IPSR_GPSR(IP1_3_0, A8),
2704 IP1_3_0 ))
H A Dpfc-r8a77990.c129 #define GPSR2_9 F_(QSPI1_IO2, IP1_3_0)
222 #define IP1_3_0 FM(QSPI1_IO2) FM(RIF2_D1_A) FM(HTX3_C) FM(VI4_DATA3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) macro
386 FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
586 PINMUX_IPSR_GPSR(IP1_3_0, QSPI1_IO2),
587 PINMUX_IPSR_MSEL(IP1_3_0, RIF2_D1_A, SEL_DRIF2_0),
588 PINMUX_IPSR_GPSR(IP1_3_0, HTX3_C),
589 PINMUX_IPSR_MSEL(IP1_3_0, VI4_DATA3_A, SEL_VIN4_0),
4806 IP1_3_0 ))
H A Dpfc-r8a77951.c142 #define GPSR2_2 F_(IRQ2, IP1_3_0)
262 #define IP1_3_0 FM(IRQ2) FM(QCPV_QDE) F_(0, 0) FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(VI4_DATA2_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SYNC_E) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) macro
445 FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
690 PINMUX_IPSR_GPSR(IP1_3_0, IRQ2),
691 PINMUX_IPSR_GPSR(IP1_3_0, QCPV_QDE),
692 PINMUX_IPSR_GPSR(IP1_3_0, DU_EXODDF_DU_ODDF_DISP_CDE),
693 PINMUX_IPSR_MSEL(IP1_3_0, VI4_DATA2_B, SEL_VIN4_1),
694 PINMUX_IPSR_MSEL(IP1_3_0, PWM3_B, SEL_PWM3_1),
695 PINMUX_IPSR_MSEL(IP1_3_0, MSIOF3_SYNC_
[all...]
H A Dpfc-r8a77965.c147 #define GPSR2_2 F_(IRQ2, IP1_3_0)
267 #define IP1_3_0 FM(IRQ2) FM(QCPV_QDE) F_(0, 0) FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(VI4_DATA2_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SYNC_E) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) macro
450 FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
696 PINMUX_IPSR_GPSR(IP1_3_0, IRQ2),
697 PINMUX_IPSR_GPSR(IP1_3_0, QCPV_QDE),
698 PINMUX_IPSR_GPSR(IP1_3_0, DU_EXODDF_DU_ODDF_DISP_CDE),
699 PINMUX_IPSR_MSEL(IP1_3_0, VI4_DATA2_B, SEL_VIN4_1),
700 PINMUX_IPSR_MSEL(IP1_3_0, PWM3_B, SEL_PWM3_1),
701 PINMUX_IPSR_MSEL(IP1_3_0, MSIOF3_SYNC_
[all...]
H A Dpfc-r8a7796.c147 #define GPSR2_2 F_(IRQ2, IP1_3_0)
267 #define IP1_3_0 FM(IRQ2) FM(QCPV_QDE) F_(0, 0) FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(VI4_DATA2_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SYNC_E) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) macro
450 FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
695 PINMUX_IPSR_GPSR(IP1_3_0, IRQ2),
696 PINMUX_IPSR_GPSR(IP1_3_0, QCPV_QDE),
697 PINMUX_IPSR_GPSR(IP1_3_0, DU_EXODDF_DU_ODDF_DISP_CDE),
698 PINMUX_IPSR_MSEL(IP1_3_0, VI4_DATA2_B, SEL_VIN4_1),
699 PINMUX_IPSR_MSEL(IP1_3_0, PWM3_B, SEL_PWM3_1),
700 PINMUX_IPSR_MSEL(IP1_3_0, MSIOF3_SYNC_
[all...]
H A Dpfc-r8a7790.c862 PINMUX_IPSR_GPSR(IP1_3_0, D9),
863 PINMUX_IPSR_MSEL(IP1_3_0, SCIFA1_RXD_C, SEL_SCIFA1_2),
864 PINMUX_IPSR_GPSR(IP1_3_0, AVB_TXD1),
865 PINMUX_IPSR_MSEL(IP1_3_0, VI0_G1, SEL_VI0_0),
866 PINMUX_IPSR_MSEL(IP1_3_0, VI0_G1_B, SEL_VI0_1),
867 PINMUX_IPSR_MSEL(IP1_3_0, VI2_DATA1_VI2_B1, SEL_VI2_0),
5192 /* IP1_3_0 [4] */
H A Dpfc-r8a77470.c578 PINMUX_IPSR_GPSR(IP1_3_0, MMC0_D4),
579 PINMUX_IPSR_GPSR(IP1_3_0, SD1_CD),
2723 /* IP1_3_0 [4] */

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