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Searched refs:IP1_15_12 (Results 1 - 17 of 17) sorted by relevance

/kernel/linux/linux-5.10/drivers/pinctrl/renesas/
H A Dpfc-r8a77970.c45 #define GPSR0_11 F_(DU_DG7, IP1_15_12)
164 #define IP1_15_12 FM(DU_DG7) F_(0, 0) F_(0, 0) FM(A11) FM(IRQ1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) macro
262 FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
430 PINMUX_IPSR_GPSR(IP1_15_12, DU_DG7),
431 PINMUX_IPSR_GPSR(IP1_15_12, A11),
432 PINMUX_IPSR_GPSR(IP1_15_12, IRQ1),
2355 IP1_15_12
H A Dpfc-r8a77980.c46 #define GPSR0_11 F_(DU_DG7, IP1_15_12)
197 #define IP1_15_12 FM(DU_DG7) FM(HRX0_A) F_(0, 0) FM(A11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) macro
313 FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
506 PINMUX_IPSR_GPSR(IP1_15_12, DU_DG7),
507 PINMUX_IPSR_MSEL(IP1_15_12, HRX0_A, SEL_HSCIF0_0),
508 PINMUX_IPSR_GPSR(IP1_15_12, A11),
2777 IP1_15_12
H A Dpfc-r8a77995.c73 #define GPSR1_4 F_(DU_DB4, IP1_15_12)
210 #define IP1_15_12 FM(DU_DB4) FM(LCDOUT4) FM(RX5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) macro
352 FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
566 PINMUX_IPSR_GPSR(IP1_15_12, DU_DB4),
567 PINMUX_IPSR_GPSR(IP1_15_12, LCDOUT4),
568 PINMUX_IPSR_MSEL(IP1_15_12, RX5_B, SEL_SCIF5_1),
2636 IP1_15_12
H A Dpfc-r8a77990.c126 #define GPSR2_12 F_(RPC_INT_N, IP1_15_12)
225 #define IP1_15_12 FM(RPC_INT_N) FM(RIF3_D0_A) FM(HCTS3_N_C) FM(VI4_DATA6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) macro
389 FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
600 PINMUX_IPSR_GPSR(IP1_15_12, RPC_INT_N),
601 PINMUX_IPSR_MSEL(IP1_15_12, RIF3_D0_A, SEL_DRIF3_0),
602 PINMUX_IPSR_MSEL(IP1_15_12, HCTS3_N_C, SEL_HSCIF3_2),
603 PINMUX_IPSR_MSEL(IP1_15_12, VI4_DATA6_A, SEL_VIN4_0),
4783 IP1_15_12
H A Dpfc-r8a77951.c140 #define GPSR2_5 F_(IRQ5, IP1_15_12)
266 #define IP1_15_12 FM(IRQ5) FM(QSTB_QHE) F_(0, 0) FM(DU_EXVSYNC_DU_VSYNC) FM(VI4_DATA5_B) FM(FSCLKST2_N_B) F_(0, 0) FM(MSIOF3_TXD_E) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) macro
449 FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
712 PINMUX_IPSR_GPSR(IP1_15_12, IRQ5),
713 PINMUX_IPSR_GPSR(IP1_15_12, QSTB_QHE),
714 PINMUX_IPSR_GPSR(IP1_15_12, DU_EXVSYNC_DU_VSYNC),
715 PINMUX_IPSR_MSEL(IP1_15_12, VI4_DATA5_B, SEL_VIN4_1),
716 PINMUX_IPSR_MSEL(IP1_15_12, PWM6_B, SEL_PWM6_1),
717 PINMUX_IPSR_GPSR(IP1_15_12, FSCLKST2_N_
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H A Dpfc-r8a77965.c145 #define GPSR2_5 F_(IRQ5, IP1_15_12)
271 #define IP1_15_12 FM(IRQ5) FM(QSTB_QHE) F_(0, 0) FM(DU_EXVSYNC_DU_VSYNC) FM(VI4_DATA5_B) FM(FSCLKST2_N_B) F_(0, 0) FM(MSIOF3_TXD_E) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) macro
454 FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
718 PINMUX_IPSR_GPSR(IP1_15_12, IRQ5),
719 PINMUX_IPSR_GPSR(IP1_15_12, QSTB_QHE),
720 PINMUX_IPSR_GPSR(IP1_15_12, DU_EXVSYNC_DU_VSYNC),
721 PINMUX_IPSR_MSEL(IP1_15_12, VI4_DATA5_B, SEL_VIN4_1),
722 PINMUX_IPSR_MSEL(IP1_15_12, PWM6_B, SEL_PWM6_1),
723 PINMUX_IPSR_GPSR(IP1_15_12, FSCLKST2_N_
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H A Dpfc-r8a77470.c578 PINMUX_IPSR_GPSR(IP1_15_12, D1),
579 PINMUX_IPSR_MSEL(IP1_15_12, SDA3_B, SEL_I2C03_1),
580 PINMUX_IPSR_MSEL(IP1_15_12, TX5_B, SEL_SCIF5_1),
581 PINMUX_IPSR_MSEL(IP1_15_12, MSIOF2_TXD_C, SEL_MSIOF2_2),
582 PINMUX_IPSR_MSEL(IP1_15_12, SSI_WS5_B, SEL_SSI5_1),
2791 /* IP1_15_12 [4] */
H A Dpfc-r8a7796.c145 #define GPSR2_5 F_(IRQ5, IP1_15_12)
271 #define IP1_15_12 FM(IRQ5) FM(QSTB_QHE) F_(0, 0) FM(DU_EXVSYNC_DU_VSYNC) FM(VI4_DATA5_B) F_(0, 0) F_(0, 0) FM(MSIOF3_TXD_E) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) macro
454 FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
717 PINMUX_IPSR_GPSR(IP1_15_12, IRQ5),
718 PINMUX_IPSR_GPSR(IP1_15_12, QSTB_QHE),
719 PINMUX_IPSR_GPSR(IP1_15_12, DU_EXVSYNC_DU_VSYNC),
720 PINMUX_IPSR_MSEL(IP1_15_12, VI4_DATA5_B, SEL_VIN4_1),
721 PINMUX_IPSR_MSEL(IP1_15_12, PWM6_B, SEL_PWM6_1),
722 PINMUX_IPSR_MSEL(IP1_15_12, MSIOF3_TXD_
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H A Dpfc-r8a77950.c139 #define GPSR2_5 F_(IRQ5, IP1_15_12)
265 #define IP1_15_12 FM(IRQ5) FM(QSTB_QHE) FM(A23) FM(DU_EXVSYNC_DU_VSYNC) FM(VI4_DATA5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) macro
439 FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
703 PINMUX_IPSR_GPSR(IP1_15_12, IRQ5),
704 PINMUX_IPSR_GPSR(IP1_15_12, QSTB_QHE),
705 PINMUX_IPSR_GPSR(IP1_15_12, A23),
706 PINMUX_IPSR_GPSR(IP1_15_12, DU_EXVSYNC_DU_VSYNC),
707 PINMUX_IPSR_MSEL(IP1_15_12, VI4_DATA5_B, SEL_VIN4_1),
708 PINMUX_IPSR_MSEL(IP1_15_12, PWM6_
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/kernel/linux/linux-6.6/drivers/pinctrl/renesas/
H A Dpfc-r8a77970.c56 #define GPSR0_11 F_(DU_DG7, IP1_15_12)
175 #define IP1_15_12 FM(DU_DG7) F_(0, 0) F_(0, 0) FM(A11) FM(IRQ1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) macro
272 FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
439 PINMUX_IPSR_GPSR(IP1_15_12, DU_DG7),
440 PINMUX_IPSR_GPSR(IP1_15_12, A11),
441 PINMUX_IPSR_GPSR(IP1_15_12, IRQ1),
2247 IP1_15_12
H A Dpfc-r8a77995.c84 #define GPSR1_4 F_(DU_DB4, IP1_15_12)
221 #define IP1_15_12 FM(DU_DB4) FM(LCDOUT4) FM(RX5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) macro
363 FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
577 PINMUX_IPSR_GPSR(IP1_15_12, DU_DB4),
578 PINMUX_IPSR_GPSR(IP1_15_12, LCDOUT4),
579 PINMUX_IPSR_MSEL(IP1_15_12, RX5_B, SEL_SCIF5_1),
2688 IP1_15_12
H A Dpfc-r8a77980.c58 #define GPSR0_11 F_(DU_DG7, IP1_15_12)
209 #define IP1_15_12 FM(DU_DG7) FM(HRX0_A) F_(0, 0) FM(A11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) macro
322 FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
515 PINMUX_IPSR_GPSR(IP1_15_12, DU_DG7),
516 PINMUX_IPSR_MSEL(IP1_15_12, HRX0_A, SEL_HSCIF0_0),
517 PINMUX_IPSR_GPSR(IP1_15_12, A11),
2701 IP1_15_12
H A Dpfc-r8a77990.c126 #define GPSR2_12 F_(RPC_INT_N, IP1_15_12)
225 #define IP1_15_12 FM(RPC_INT_N) FM(RIF3_D0_A) FM(HCTS3_N_C) FM(VI4_DATA6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) macro
389 FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
601 PINMUX_IPSR_GPSR(IP1_15_12, RPC_INT_N),
602 PINMUX_IPSR_MSEL(IP1_15_12, RIF3_D0_A, SEL_DRIF3_0),
603 PINMUX_IPSR_MSEL(IP1_15_12, HCTS3_N_C, SEL_HSCIF3_2),
604 PINMUX_IPSR_MSEL(IP1_15_12, VI4_DATA6_A, SEL_VIN4_0),
4803 IP1_15_12
H A Dpfc-r8a77951.c139 #define GPSR2_5 F_(IRQ5, IP1_15_12)
265 #define IP1_15_12 FM(IRQ5) FM(QSTB_QHE) F_(0, 0) FM(DU_EXVSYNC_DU_VSYNC) FM(VI4_DATA5_B) FM(FSCLKST2_N_B) F_(0, 0) FM(MSIOF3_TXD_E) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) macro
448 FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
711 PINMUX_IPSR_GPSR(IP1_15_12, IRQ5),
712 PINMUX_IPSR_GPSR(IP1_15_12, QSTB_QHE),
713 PINMUX_IPSR_GPSR(IP1_15_12, DU_EXVSYNC_DU_VSYNC),
714 PINMUX_IPSR_MSEL(IP1_15_12, VI4_DATA5_B, SEL_VIN4_1),
715 PINMUX_IPSR_MSEL(IP1_15_12, PWM6_B, SEL_PWM6_1),
716 PINMUX_IPSR_GPSR(IP1_15_12, FSCLKST2_N_
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H A Dpfc-r8a77965.c144 #define GPSR2_5 F_(IRQ5, IP1_15_12)
270 #define IP1_15_12 FM(IRQ5) FM(QSTB_QHE) F_(0, 0) FM(DU_EXVSYNC_DU_VSYNC) FM(VI4_DATA5_B) FM(FSCLKST2_N_B) F_(0, 0) FM(MSIOF3_TXD_E) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) macro
453 FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
717 PINMUX_IPSR_GPSR(IP1_15_12, IRQ5),
718 PINMUX_IPSR_GPSR(IP1_15_12, QSTB_QHE),
719 PINMUX_IPSR_GPSR(IP1_15_12, DU_EXVSYNC_DU_VSYNC),
720 PINMUX_IPSR_MSEL(IP1_15_12, VI4_DATA5_B, SEL_VIN4_1),
721 PINMUX_IPSR_MSEL(IP1_15_12, PWM6_B, SEL_PWM6_1),
722 PINMUX_IPSR_GPSR(IP1_15_12, FSCLKST2_N_
[all...]
H A Dpfc-r8a77470.c588 PINMUX_IPSR_GPSR(IP1_15_12, D1),
589 PINMUX_IPSR_MSEL(IP1_15_12, SDA3_B, SEL_I2C03_1),
590 PINMUX_IPSR_MSEL(IP1_15_12, TX5_B, SEL_SCIF5_1),
591 PINMUX_IPSR_MSEL(IP1_15_12, MSIOF2_TXD_C, SEL_MSIOF2_2),
592 PINMUX_IPSR_MSEL(IP1_15_12, SSI_WS5_B, SEL_SSI5_1),
2714 /* IP1_15_12 [4] */
H A Dpfc-r8a7796.c144 #define GPSR2_5 F_(IRQ5, IP1_15_12)
270 #define IP1_15_12 FM(IRQ5) FM(QSTB_QHE) F_(0, 0) FM(DU_EXVSYNC_DU_VSYNC) FM(VI4_DATA5_B) F_(0, 0) F_(0, 0) FM(MSIOF3_TXD_E) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) macro
453 FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
716 PINMUX_IPSR_GPSR(IP1_15_12, IRQ5),
717 PINMUX_IPSR_GPSR(IP1_15_12, QSTB_QHE),
718 PINMUX_IPSR_GPSR(IP1_15_12, DU_EXVSYNC_DU_VSYNC),
719 PINMUX_IPSR_MSEL(IP1_15_12, VI4_DATA5_B, SEL_VIN4_1),
720 PINMUX_IPSR_MSEL(IP1_15_12, PWM6_B, SEL_PWM6_1),
721 PINMUX_IPSR_MSEL(IP1_15_12, MSIOF3_TXD_
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