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Searched refs:INT_MASK_CSR (Results 1 - 10 of 10) sorted by relevance

/kernel/linux/linux-5.10/drivers/net/wireless/ralink/rt2x00/
H A Drt2800mmio.c207 reg = rt2x00mmio_register_read(rt2x00dev, INT_MASK_CSR); in rt2800mmio_enable_interrupt()
209 rt2x00mmio_register_write(rt2x00dev, INT_MASK_CSR, reg); in rt2800mmio_enable_interrupt()
342 * Since INT_MASK_CSR and INT_SOURCE_CSR use the same bits in rt2800mmio_interrupt()
372 reg = rt2x00mmio_register_read(rt2x00dev, INT_MASK_CSR); in rt2800mmio_interrupt()
374 rt2x00mmio_register_write(rt2x00dev, INT_MASK_CSR, reg); in rt2800mmio_interrupt()
405 rt2x00mmio_register_write(rt2x00dev, INT_MASK_CSR, reg); in rt2800mmio_toggle_irq()
H A Drt61pci.c1645 reg = rt2x00mmio_register_read(rt2x00dev, INT_MASK_CSR); in rt61pci_toggle_irq()
1651 rt2x00mmio_register_write(rt2x00dev, INT_MASK_CSR, reg); in rt61pci_toggle_irq()
2168 reg = rt2x00mmio_register_read(rt2x00dev, INT_MASK_CSR); in rt61pci_enable_interrupt()
2170 rt2x00mmio_register_write(rt2x00dev, INT_MASK_CSR, reg); in rt61pci_enable_interrupt()
2270 * Since INT_MASK_CSR and INT_SOURCE_CSR use the same bits in rt61pci_interrupt()
2283 reg = rt2x00mmio_register_read(rt2x00dev, INT_MASK_CSR); in rt61pci_interrupt()
2285 rt2x00mmio_register_write(rt2x00dev, INT_MASK_CSR, reg); in rt61pci_interrupt()
H A Drt61pci.h968 * INT_MASK_CSR: Interrupt MASK register. 1: the interrupt is mask OFF.
971 #define INT_MASK_CSR 0x346c macro
H A Drt2800.h321 * INT_MASK_CSR: Interrupt MASK register. 1: the interrupt is mask OFF.
323 #define INT_MASK_CSR 0x0204 macro
/kernel/linux/linux-6.6/drivers/net/wireless/ralink/rt2x00/
H A Drt2800mmio.c207 reg = rt2x00mmio_register_read(rt2x00dev, INT_MASK_CSR); in rt2800mmio_enable_interrupt()
209 rt2x00mmio_register_write(rt2x00dev, INT_MASK_CSR, reg); in rt2800mmio_enable_interrupt()
342 * Since INT_MASK_CSR and INT_SOURCE_CSR use the same bits in rt2800mmio_interrupt()
372 reg = rt2x00mmio_register_read(rt2x00dev, INT_MASK_CSR); in rt2800mmio_interrupt()
374 rt2x00mmio_register_write(rt2x00dev, INT_MASK_CSR, reg); in rt2800mmio_interrupt()
405 rt2x00mmio_register_write(rt2x00dev, INT_MASK_CSR, reg); in rt2800mmio_toggle_irq()
H A Drt61pci.c1645 reg = rt2x00mmio_register_read(rt2x00dev, INT_MASK_CSR); in rt61pci_toggle_irq()
1651 rt2x00mmio_register_write(rt2x00dev, INT_MASK_CSR, reg); in rt61pci_toggle_irq()
2168 reg = rt2x00mmio_register_read(rt2x00dev, INT_MASK_CSR); in rt61pci_enable_interrupt()
2170 rt2x00mmio_register_write(rt2x00dev, INT_MASK_CSR, reg); in rt61pci_enable_interrupt()
2270 * Since INT_MASK_CSR and INT_SOURCE_CSR use the same bits in rt61pci_interrupt()
2283 reg = rt2x00mmio_register_read(rt2x00dev, INT_MASK_CSR); in rt61pci_interrupt()
2285 rt2x00mmio_register_write(rt2x00dev, INT_MASK_CSR, reg); in rt61pci_interrupt()
H A Drt61pci.h968 * INT_MASK_CSR: Interrupt MASK register. 1: the interrupt is mask OFF.
971 #define INT_MASK_CSR 0x346c macro
H A Drt2800.h321 * INT_MASK_CSR: Interrupt MASK register. 1: the interrupt is mask OFF.
323 #define INT_MASK_CSR 0x0204 macro
/kernel/linux/linux-6.6/drivers/net/wireless/mediatek/mt76/mt7915/
H A Dmmio.c22 [INT_MASK_CSR] = 0xd7014,
56 [INT_MASK_CSR] = 0xd4204,
90 [INT_MASK_CSR] = 0x24204,
H A Dregs.h17 INT_MASK_CSR, enumerator
701 #define MT_INT_MASK_CSR __REG(INT_MASK_CSR)

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