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Searched refs:IMX8ULP_CLK_SPLL3_PFD0_DIV2 (Results 1 - 3 of 3) sorted by relevance

/kernel/linux/linux-6.6/include/dt-bindings/clock/
H A Dimx8ulp-clock.h23 #define IMX8ULP_CLK_SPLL3_PFD0_DIV2 16 macro
/kernel/linux/linux-6.6/scripts/dtc/include-prefixes/dt-bindings/clock/
H A Dimx8ulp-clock.h23 #define IMX8ULP_CLK_SPLL3_PFD0_DIV2 16 macro
/kernel/linux/linux-6.6/drivers/clk/imx/
H A Dclk-imx8ulp.c188 clks[IMX8ULP_CLK_SPLL3_PFD0_DIV2] = imx_clk_hw_divider("spll3_pfd0_div2", "spll3_pfd0_div2_gate", base + 0x608, 8, 6); in imx8ulp_clk_cgc1_init()

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