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Searched refs:IMX7ULP_CLK_SPLL_PRE_DIV (Results 1 - 6 of 6) sorted by relevance

/kernel/linux/linux-5.10/scripts/dtc/include-prefixes/dt-bindings/clock/
H A Dimx7ulp-clock.h18 #define IMX7ULP_CLK_SPLL_PRE_DIV 5 macro
/kernel/linux/linux-5.10/include/dt-bindings/clock/
H A Dimx7ulp-clock.h18 #define IMX7ULP_CLK_SPLL_PRE_DIV 5 macro
/kernel/linux/linux-6.6/include/dt-bindings/clock/
H A Dimx7ulp-clock.h18 #define IMX7ULP_CLK_SPLL_PRE_DIV 5 macro
/kernel/linux/linux-6.6/scripts/dtc/include-prefixes/dt-bindings/clock/
H A Dimx7ulp-clock.h18 #define IMX7ULP_CLK_SPLL_PRE_DIV 5 macro
/kernel/linux/linux-5.10/drivers/clk/imx/
H A Dclk-imx7ulp.c78 hws[IMX7ULP_CLK_SPLL_PRE_DIV] = imx_clk_hw_divider_flags("spll_pre_div", "spll_pre_sel", base + 0x608, 8, 3, CLK_SET_RATE_GATE); in imx7ulp_clk_scg1_init()
/kernel/linux/linux-6.6/drivers/clk/imx/
H A Dclk-imx7ulp.c78 hws[IMX7ULP_CLK_SPLL_PRE_DIV] = imx_clk_hw_divider_flags("spll_pre_div", "spll_pre_sel", base + 0x608, 8, 3, CLK_SET_RATE_GATE); in imx7ulp_clk_scg1_init()

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