Searched refs:IMX7ULP_CLK_DDR_DIV (Results 1 - 6 of 6) sorted by relevance
| /kernel/linux/linux-5.10/scripts/dtc/include-prefixes/dt-bindings/clock/ |
| H A D | imx7ulp-clock.h | 45 #define IMX7ULP_CLK_DDR_DIV 32 macro
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| /kernel/linux/linux-5.10/include/dt-bindings/clock/ |
| H A D | imx7ulp-clock.h | 45 #define IMX7ULP_CLK_DDR_DIV 32 macro
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| /kernel/linux/linux-6.6/include/dt-bindings/clock/ |
| H A D | imx7ulp-clock.h | 45 #define IMX7ULP_CLK_DDR_DIV 32 macro
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| /kernel/linux/linux-6.6/scripts/dtc/include-prefixes/dt-bindings/clock/ |
| H A D | imx7ulp-clock.h | 45 #define IMX7ULP_CLK_DDR_DIV 32 macro
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| /kernel/linux/linux-5.10/drivers/clk/imx/ |
| H A D | clk-imx7ulp.c | 115 hws[IMX7ULP_CLK_DDR_DIV] = imx_clk_hw_divider_gate("ddr_clk", "ddr_sel", CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, base + 0x30, 0, 3, in imx7ulp_clk_scg1_init()
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| /kernel/linux/linux-6.6/drivers/clk/imx/ |
| H A D | clk-imx7ulp.c | 115 hws[IMX7ULP_CLK_DDR_DIV] = imx_clk_hw_divider_gate("ddr_clk", "ddr_sel", CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, base + 0x30, 0, 3, in imx7ulp_clk_scg1_init()
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