Searched refs:ICC_SRE_EL1 (Results 1 - 3 of 3) sorted by relevance
| /kernel/liteos_a/arch/arm/include/ |
| H A D | gic_v3.h | 45 #define ICC_SRE_EL1 "S3_0_C12_C12_5" macro
151 __asm__ volatile("mrs %0, " ICC_SRE_EL1 : "=r"(temp)); in GiccGetSre()
161 __asm__ volatile("msr " ICC_SRE_EL1 ", %0" ::"r"(val)); in GiccSetSre()
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| /kernel/linux/linux-6.6/arch/arm64/kvm/hyp/ |
| H A D | vgic-v3-sr.c | 263 * VFIQEn is RES1 if ICC_SRE_EL1.SRE is 1. This causes a in __vgic_v3_activate_traps()
266 * consequences. So we must make sure that ICC_SRE_EL1 has in __vgic_v3_activate_traps()
273 write_gicreg(0, ICC_SRE_EL1); in __vgic_v3_activate_traps()
321 write_gicreg(1, ICC_SRE_EL1); in __vgic_v3_deactivate_traps()
416 u64 val, sre = read_gicreg(ICC_SRE_EL1); in __vgic_v3_get_gic_config()
434 * that to be able to set ICC_SRE_EL1.SRE to 0, all the in __vgic_v3_get_gic_config()
439 write_gicreg(0, ICC_SRE_EL1); in __vgic_v3_get_gic_config()
442 val = read_gicreg(ICC_SRE_EL1); in __vgic_v3_get_gic_config()
444 write_gicreg(sre, ICC_SRE_EL1); in __vgic_v3_get_gic_config()
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| /kernel/linux/linux-5.10/arch/arm64/kvm/hyp/ |
| H A D | vgic-v3-sr.c | 261 * VFIQEn is RES1 if ICC_SRE_EL1.SRE is 1. This causes a in __vgic_v3_activate_traps()
264 * consequences. So we must make sure that ICC_SRE_EL1 has in __vgic_v3_activate_traps()
271 write_gicreg(0, ICC_SRE_EL1); in __vgic_v3_activate_traps()
319 write_gicreg(1, ICC_SRE_EL1); in __vgic_v3_deactivate_traps()
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