Searched refs:HALF_SLICE_CHICKEN2 (Results 1 - 10 of 10) sorted by relevance
| /kernel/linux/linux-5.10/drivers/gpu/drm/i915/gvt/ |
| H A D | mmio_context.c | 108 {RCS0, HALF_SLICE_CHICKEN2, 0xffff, true}, /* 0xe180 */
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| H A D | handlers.c | 2923 MMIO_DFH(HALF_SLICE_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); in init_bdw_mmio_info()
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| /kernel/linux/linux-5.10/drivers/gpu/drm/i915/ |
| H A D | i915_perf.c | 3841 return REG_EQUAL(addr, HALF_SLICE_CHICKEN2) || in gen7_is_valid_mux_addr()
3899 /* HALF_SLICE_CHICKEN2 is programmed with a the in mask_reg_value()
3903 if (REG_EQUAL(reg, HALF_SLICE_CHICKEN2)) in mask_reg_value()
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| H A D | i915_reg.h | 9374 #define HALF_SLICE_CHICKEN2 _MMIO(0xe180) macro
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| /kernel/linux/linux-5.10/drivers/gpu/drm/i915/gt/ |
| H A D | intel_workarounds.c | 411 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE); in gen9_ctx_workarounds_init()
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| /kernel/linux/linux-6.6/drivers/gpu/drm/i915/gt/ |
| H A D | intel_gt_regs.h | 1139 #define HALF_SLICE_CHICKEN2 MCR_REG(0xe180) macro
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| H A D | intel_workarounds.c | 508 wa_mcr_masked_en(wal, HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE); in gen9_ctx_workarounds_init()
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| /kernel/linux/linux-6.6/drivers/gpu/drm/i915/ |
| H A D | intel_gvt_mmio_table.c | 841 MMIO_D(HALF_SLICE_CHICKEN2); in iterate_bdw_plus_mmio()
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| H A D | i915_perf.c | 4465 { .start = 0xe180, .end = 0xe180 }, /* HALF_SLICE_CHICKEN2 */
4575 /* HALF_SLICE_CHICKEN2 is programmed with a the in mask_reg_value()
4579 if (REG_EQUAL(reg, HALF_SLICE_CHICKEN2)) in mask_reg_value()
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| /kernel/linux/linux-6.6/drivers/gpu/drm/i915/gvt/ |
| H A D | handlers.c | 2559 MMIO_DFH(HALF_SLICE_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); in init_bdw_mmio_info()
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