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Searched refs:GMAC_CTRL (Results 1 - 8 of 8) sorted by relevance

/kernel/linux/linux-5.10/drivers/net/ethernet/marvell/
H A Dsky2.c477 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON); in sky2_phy_init()
479 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF); in sky2_phy_init()
725 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR); in sky2_phy_power_down()
819 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR); in sky2_wol_init()
908 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR); in sky2_mac_init()
915 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR); in sky2_mac_init()
917 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET); in sky2_mac_init()
918 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR); in sky2_mac_init()
2070 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF); in sky2_hw_down()
2088 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SE in sky2_hw_down()
[all...]
H A Dskge.c193 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR); in skge_wol_init()
2074 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET); in yukon_mac_init()
2093 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON | GMC_RST_CLR); in yukon_mac_init()
2121 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF); in yukon_mac_init()
2243 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET); in yukon_stop()
2389 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF); in yukon_phy_intr()
2391 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON); in yukon_phy_intr()
H A Dskge.h850 GMAC_CTRL = 0x0f00,/* 32 bit GMAC Control Reg */ enumerator
1890 /* GMAC_CTRL 32 bit GMAC Control Reg (YUKON only) */
H A Dsky2.h1100 GMAC_CTRL = 0x0f00,/* 32 bit GMAC Control Reg */ enumerator
2013 /* GMAC_CTRL 32 bit GMAC Control Reg (YUKON only) */
/kernel/linux/linux-6.6/drivers/net/ethernet/marvell/
H A Dsky2.c476 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON); in sky2_phy_init()
478 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF); in sky2_phy_init()
724 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR); in sky2_phy_power_down()
818 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR); in sky2_wol_init()
907 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR); in sky2_mac_init()
914 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR); in sky2_mac_init()
916 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET); in sky2_mac_init()
917 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR); in sky2_mac_init()
2070 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF); in sky2_hw_down()
2088 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SE in sky2_hw_down()
[all...]
H A Dskge.c192 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR); in skge_wol_init()
2081 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET); in yukon_mac_init()
2100 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON | GMC_RST_CLR); in yukon_mac_init()
2128 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF); in yukon_mac_init()
2250 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET); in yukon_stop()
2396 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF); in yukon_phy_intr()
2398 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON); in yukon_phy_intr()
H A Dskge.h850 GMAC_CTRL = 0x0f00,/* 32 bit GMAC Control Reg */ enumerator
1890 /* GMAC_CTRL 32 bit GMAC Control Reg (YUKON only) */
H A Dsky2.h1100 GMAC_CTRL = 0x0f00,/* 32 bit GMAC Control Reg */ enumerator
2013 /* GMAC_CTRL 32 bit GMAC Control Reg (YUKON only) */

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