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Searched refs:GFX_OP_PIPE_CONTROL (Results 1 - 14 of 14) sorted by relevance

/kernel/linux/linux-5.10/drivers/gpu/drm/i915/gt/
H A Dgen6_engine_cs.c65 *cs++ = GFX_OP_PIPE_CONTROL(5); in gen6_emit_post_sync_nonzero_flush()
77 *cs++ = GFX_OP_PIPE_CONTROL(5); in gen6_emit_post_sync_nonzero_flush()
133 *cs++ = GFX_OP_PIPE_CONTROL(4); in gen6_emit_flush_rcs()
145 *cs++ = GFX_OP_PIPE_CONTROL(4); in gen6_emit_breadcrumb_rcs()
150 *cs++ = GFX_OP_PIPE_CONTROL(4); in gen6_emit_breadcrumb_rcs()
158 *cs++ = GFX_OP_PIPE_CONTROL(4); in gen6_emit_breadcrumb_rcs()
279 *cs++ = GFX_OP_PIPE_CONTROL(4); in gen7_stall_cs()
343 *cs++ = GFX_OP_PIPE_CONTROL(4); in gen7_emit_flush_rcs()
354 *cs++ = GFX_OP_PIPE_CONTROL(4); in gen7_emit_breadcrumb_rcs()
H A Dgen7_renderclear.c343 *cs++ = GFX_OP_PIPE_CONTROL(4); in gen7_emit_pipeline_flush()
359 *cs++ = GFX_OP_PIPE_CONTROL(5); in gen7_emit_pipeline_invalidate()
366 *cs++ = GFX_OP_PIPE_CONTROL(5); in gen7_emit_pipeline_invalidate()
H A Dintel_engine.h230 batch[0] = GFX_OP_PIPE_CONTROL(6) | flags0; in __gen8_emit_pipe_control()
250 *cs++ = GFX_OP_PIPE_CONTROL(6) | flags0; in __gen8_emit_write_rcs()
H A Dgen2_engine_cs.c102 *cs++ = GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE; in gen4_emit_flush_rcs()
112 *cs++ = GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE; in gen4_emit_flush_rcs()
H A Dintel_gpu_commands.h221 #define GFX_OP_PIPE_CONTROL(len) ((0x3<<29)|(0x3<<27)|(0x2<<24)|((len)-2)) macro
/kernel/linux/linux-6.6/drivers/gpu/drm/i915/gt/
H A Dgen6_engine_cs.c66 *cs++ = GFX_OP_PIPE_CONTROL(5); in gen6_emit_post_sync_nonzero_flush()
78 *cs++ = GFX_OP_PIPE_CONTROL(5); in gen6_emit_post_sync_nonzero_flush()
134 *cs++ = GFX_OP_PIPE_CONTROL(4); in gen6_emit_flush_rcs()
146 *cs++ = GFX_OP_PIPE_CONTROL(4); in gen6_emit_breadcrumb_rcs()
151 *cs++ = GFX_OP_PIPE_CONTROL(4); in gen6_emit_breadcrumb_rcs()
159 *cs++ = GFX_OP_PIPE_CONTROL(4); in gen6_emit_breadcrumb_rcs()
280 *cs++ = GFX_OP_PIPE_CONTROL(4); in gen7_stall_cs()
344 *cs++ = GFX_OP_PIPE_CONTROL(4); in gen7_emit_flush_rcs()
355 *cs++ = GFX_OP_PIPE_CONTROL(4); in gen7_emit_breadcrumb_rcs()
H A Dgen8_engine_cs.h58 batch[0] = GFX_OP_PIPE_CONTROL(6) | bit_group_0; in __gen8_emit_pipe_control()
81 *cs++ = GFX_OP_PIPE_CONTROL(6) | flags0; in __gen8_emit_write_rcs()
H A Dgen7_renderclear.c344 *cs++ = GFX_OP_PIPE_CONTROL(4); in gen7_emit_pipeline_flush()
360 *cs++ = GFX_OP_PIPE_CONTROL(5); in gen7_emit_pipeline_invalidate()
367 *cs++ = GFX_OP_PIPE_CONTROL(5); in gen7_emit_pipeline_invalidate()
H A Dgen2_engine_cs.c104 *cs++ = GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE; in gen4_emit_flush_rcs()
114 *cs++ = GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE; in gen4_emit_flush_rcs()
H A Dintel_gpu_commands.h286 #define GFX_OP_PIPE_CONTROL(len) ((0x3<<29)|(0x3<<27)|(0x2<<24)|((len)-2)) macro
/kernel/linux/linux-5.10/drivers/gpu/drm/i915/selftests/
H A Di915_perf.c168 *cs++ = GFX_OP_PIPE_CONTROL(len); in write_timestamp()
/kernel/linux/linux-6.6/drivers/gpu/drm/i915/selftests/
H A Di915_perf.c174 *cs++ = GFX_OP_PIPE_CONTROL(len); in write_timestamp()
/kernel/linux/linux-5.10/drivers/gpu/drm/i915/
H A Di915_cmd_parser.c288 CMD( GFX_OP_PIPE_CONTROL(5), S3D, !F, 0xFF, B,
/kernel/linux/linux-6.6/drivers/gpu/drm/i915/
H A Di915_cmd_parser.c297 CMD( GFX_OP_PIPE_CONTROL(5), S3D, !F, 0xFF, B,

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