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Searched refs:GENMASK_ULL (Results 1 - 25 of 448) sorted by relevance

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/kernel/linux/linux-6.6/drivers/infiniband/hw/irdma/
H A Duda_d.h19 #define IRDMA_UDA_QPSQ_INLINEDATALEN GENMASK_ULL(55, 48)
20 #define IRDMA_UDA_QPSQ_ADDFRAGCNT GENMASK_ULL(41, 38)
21 #define IRDMA_UDA_QPSQ_IPFRAGFLAGS GENMASK_ULL(43, 42)
25 #define IRDMA_UDA_QPSQ_AHIDX GENMASK_ULL(16, 0)
26 #define IRDMA_UDA_QPSQ_PROTOCOL GENMASK_ULL(23, 16)
27 #define IRDMA_UDA_QPSQ_EXTHDRLEN GENMASK_ULL(40, 32)
29 #define IRDMA_UDA_QPSQ_MACLEN GENMASK_ULL(62, 56)
31 #define IRDMA_UDA_QPSQ_IPLEN GENMASK_ULL(54, 48)
33 #define IRDMA_UDA_QPSQ_L4T GENMASK_ULL(31, 30)
35 #define IRDMA_UDA_QPSQ_IIPT GENMASK_ULL(2
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H A Ddefs.h375 #define IRDMA_CQPSQ_QHASH_VLANID GENMASK_ULL(43, 32)
376 #define IRDMA_CQPSQ_QHASH_QPN GENMASK_ULL(49, 32)
377 #define IRDMA_CQPSQ_QHASH_QS_HANDLE GENMASK_ULL(9, 0)
378 #define IRDMA_CQPSQ_QHASH_SRC_PORT GENMASK_ULL(31, 16)
379 #define IRDMA_CQPSQ_QHASH_DEST_PORT GENMASK_ULL(15, 0)
380 #define IRDMA_CQPSQ_QHASH_ADDR0 GENMASK_ULL(63, 32)
381 #define IRDMA_CQPSQ_QHASH_ADDR1 GENMASK_ULL(31, 0)
382 #define IRDMA_CQPSQ_QHASH_ADDR2 GENMASK_ULL(63, 32)
383 #define IRDMA_CQPSQ_QHASH_ADDR3 GENMASK_ULL(31, 0)
385 #define IRDMA_CQPSQ_QHASH_OPCODE GENMASK_ULL(3
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H A Dicrdma_hw.h54 #define ICRDMA_CQPSQ_STAG_PDID GENMASK_ULL(63, 46)
56 #define ICRDMA_CQPSQ_CQ_CEQID GENMASK_ULL(31, 22)
58 #define ICRDMA_CQPSQ_CQ_CQID GENMASK_ULL(18, 0)
60 #define ICRDMA_COMMIT_FPM_CQCNT GENMASK_ULL(19, 0)
/kernel/linux/linux-6.6/drivers/iommu/arm/arm-smmu-v3/
H A Darm-smmu-v3.h134 #define STRTAB_BASE_ADDR_MASK GENMASK_ULL(51, 6)
164 #define MSI_CFG0_ADDR_MASK GENMASK_ULL(51, 2)
184 #define Q_BASE_ADDR_MASK GENMASK_ULL(51, 5)
205 #define STRTAB_L1_DESC_SPAN GENMASK_ULL(4, 0)
206 #define STRTAB_L1_DESC_L2PTR_MASK GENMASK_ULL(51, 6)
210 #define STRTAB_STE_0_CFG GENMASK_ULL(3, 1)
216 #define STRTAB_STE_0_S1FMT GENMASK_ULL(5, 4)
219 #define STRTAB_STE_0_S1CTXPTR_MASK GENMASK_ULL(51, 6)
220 #define STRTAB_STE_0_S1CDMAX GENMASK_ULL(63, 59)
222 #define STRTAB_STE_1_S1DSS GENMASK_ULL(
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/kernel/linux/linux-5.10/drivers/iommu/arm/arm-smmu-v3/
H A Darm-smmu-v3.h128 #define STRTAB_BASE_ADDR_MASK GENMASK_ULL(51, 6)
158 #define MSI_CFG0_ADDR_MASK GENMASK_ULL(51, 2)
178 #define Q_BASE_ADDR_MASK GENMASK_ULL(51, 5)
199 #define STRTAB_L1_DESC_SPAN GENMASK_ULL(4, 0)
200 #define STRTAB_L1_DESC_L2PTR_MASK GENMASK_ULL(51, 6)
204 #define STRTAB_STE_0_CFG GENMASK_ULL(3, 1)
210 #define STRTAB_STE_0_S1FMT GENMASK_ULL(5, 4)
213 #define STRTAB_STE_0_S1CTXPTR_MASK GENMASK_ULL(51, 6)
214 #define STRTAB_STE_0_S1CDMAX GENMASK_ULL(63, 59)
216 #define STRTAB_STE_1_S1DSS GENMASK_ULL(
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/kernel/linux/linux-6.6/drivers/net/ethernet/marvell/octeontx2/af/
H A Dcgx_fw_if.h170 #define EVTREG_ID GENMASK_ULL(8, 3)
177 #define EVTREG_ERRTYPE GENMASK_ULL(18, 9)
182 #define RESP_MAJOR_VER GENMASK_ULL(12, 9)
183 #define RESP_MINOR_VER GENMASK_ULL(16, 13)
188 #define RESP_MAC_ADDR GENMASK_ULL(56, 9)
193 #define RESP_MKEX_PRFL_SIZE GENMASK_ULL(63, 9)
198 #define RESP_MKEX_PRFL_ADDR GENMASK_ULL(63, 9)
203 #define RESP_FWD_BASE GENMASK_ULL(56, 9)
204 #define RESP_LINKSTAT_LMAC_TYPE GENMASK_ULL(35, 28)
228 #define RESP_LINKSTAT_UP GENMASK_ULL(
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H A Dnpc.h401 #define NPC_EXACT_NIBBLE GENMASK_ULL(43, 40)
407 #define NPC_EXACT_NIBBLE_INDEX GENMASK_ULL(43, 41)
410 #define NPC_EXACT_RESULT_OPC GENMASK_ULL(2, 1)
411 #define NPC_EXACT_RESULT_WAY GENMASK_ULL(4, 3)
412 #define NPC_EXACT_RESULT_IDX GENMASK_ULL(15, 5)
415 #define NPC_PARSE_NIBBLE GENMASK_ULL(30, 0)
418 #define NPC_PARSE_NIBBLE_CHAN GENMASK_ULL(2, 0)
420 #define NPC_PARSE_NIBBLE_ERRCODE GENMASK_ULL(5, 4)
422 #define NPC_PARSE_NIBBLE_LA_FLAGS GENMASK_ULL(8, 7)
424 #define NPC_PARSE_NIBBLE_LB_FLAGS GENMASK_ULL(1
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H A Drvu_npc_hash.h104 GENMASK_ULL(63, 0),
105 GENMASK_ULL(63, 0),
108 GENMASK_ULL(63, 0),
109 GENMASK_ULL(63, 0),
115 GENMASK_ULL(63, 0),
116 GENMASK_ULL(63, 0),
119 GENMASK_ULL(63, 0),
120 GENMASK_ULL(63, 0),
127 [0] = GENMASK_ULL(63, 32), /* MSB 32 bit is mask and LSB 32 bit is offset. */
128 [1] = GENMASK_ULL(6
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/kernel/linux/linux-5.10/drivers/platform/mellanox/
H A Dmlxbf-tmfifo-regs.h18 #define MLXBF_TMFIFO_TX_STS__COUNT_RMASK GENMASK_ULL(8, 0)
19 #define MLXBF_TMFIFO_TX_STS__COUNT_MASK GENMASK_ULL(8, 0)
25 #define MLXBF_TMFIFO_TX_CTL__LWM_RMASK GENMASK_ULL(7, 0)
26 #define MLXBF_TMFIFO_TX_CTL__LWM_MASK GENMASK_ULL(7, 0)
30 #define MLXBF_TMFIFO_TX_CTL__HWM_RMASK GENMASK_ULL(7, 0)
31 #define MLXBF_TMFIFO_TX_CTL__HWM_MASK GENMASK_ULL(15, 8)
35 #define MLXBF_TMFIFO_TX_CTL__MAX_ENTRIES_RMASK GENMASK_ULL(8, 0)
36 #define MLXBF_TMFIFO_TX_CTL__MAX_ENTRIES_MASK GENMASK_ULL(40, 32)
43 #define MLXBF_TMFIFO_RX_STS__COUNT_RMASK GENMASK_ULL(8, 0)
44 #define MLXBF_TMFIFO_RX_STS__COUNT_MASK GENMASK_ULL(
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/kernel/linux/linux-6.6/drivers/platform/mellanox/
H A Dmlxbf-tmfifo-regs.h18 #define MLXBF_TMFIFO_TX_STS__COUNT_RMASK GENMASK_ULL(8, 0)
19 #define MLXBF_TMFIFO_TX_STS__COUNT_MASK GENMASK_ULL(8, 0)
25 #define MLXBF_TMFIFO_TX_CTL__LWM_RMASK GENMASK_ULL(7, 0)
26 #define MLXBF_TMFIFO_TX_CTL__LWM_MASK GENMASK_ULL(7, 0)
30 #define MLXBF_TMFIFO_TX_CTL__HWM_RMASK GENMASK_ULL(7, 0)
31 #define MLXBF_TMFIFO_TX_CTL__HWM_MASK GENMASK_ULL(15, 8)
35 #define MLXBF_TMFIFO_TX_CTL__MAX_ENTRIES_RMASK GENMASK_ULL(8, 0)
36 #define MLXBF_TMFIFO_TX_CTL__MAX_ENTRIES_MASK GENMASK_ULL(40, 32)
43 #define MLXBF_TMFIFO_RX_STS__COUNT_RMASK GENMASK_ULL(8, 0)
44 #define MLXBF_TMFIFO_RX_STS__COUNT_MASK GENMASK_ULL(
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/kernel/linux/linux-5.10/drivers/mmc/host/
H A Dcavium.h121 #define MIO_EMM_DMA_FIFO_CFG_INT_LVL GENMASK_ULL(12, 8)
122 #define MIO_EMM_DMA_FIFO_CFG_COUNT GENMASK_ULL(4, 0)
130 #define MIO_EMM_DMA_FIFO_CMD_SIZE GENMASK_ULL(55, 36)
133 #define MIO_EMM_CMD_BUS_ID GENMASK_ULL(61, 60)
136 #define MIO_EMM_CMD_OFFSET GENMASK_ULL(54, 49)
137 #define MIO_EMM_CMD_CTYPE_XOR GENMASK_ULL(42, 41)
138 #define MIO_EMM_CMD_RTYPE_XOR GENMASK_ULL(40, 38)
139 #define MIO_EMM_CMD_IDX GENMASK_ULL(37, 32)
140 #define MIO_EMM_CMD_ARG GENMASK_ULL(31, 0)
143 #define MIO_EMM_DMA_BUS_ID GENMASK_ULL(6
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/kernel/linux/linux-6.6/drivers/mmc/host/
H A Dcavium.h121 #define MIO_EMM_DMA_FIFO_CFG_INT_LVL GENMASK_ULL(12, 8)
122 #define MIO_EMM_DMA_FIFO_CFG_COUNT GENMASK_ULL(4, 0)
130 #define MIO_EMM_DMA_FIFO_CMD_SIZE GENMASK_ULL(55, 36)
133 #define MIO_EMM_CMD_BUS_ID GENMASK_ULL(61, 60)
136 #define MIO_EMM_CMD_OFFSET GENMASK_ULL(54, 49)
137 #define MIO_EMM_CMD_CTYPE_XOR GENMASK_ULL(42, 41)
138 #define MIO_EMM_CMD_RTYPE_XOR GENMASK_ULL(40, 38)
139 #define MIO_EMM_CMD_IDX GENMASK_ULL(37, 32)
140 #define MIO_EMM_CMD_ARG GENMASK_ULL(31, 0)
143 #define MIO_EMM_DMA_BUS_ID GENMASK_ULL(6
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/kernel/linux/linux-5.10/drivers/net/ethernet/marvell/octeontx2/af/
H A Dcgx_fw_if.h123 #define EVTREG_ID GENMASK_ULL(8, 3)
130 #define EVTREG_ERRTYPE GENMASK_ULL(18, 9)
135 #define RESP_MAJOR_VER GENMASK_ULL(12, 9)
136 #define RESP_MINOR_VER GENMASK_ULL(16, 13)
141 #define RESP_MAC_ADDR GENMASK_ULL(56, 9)
146 #define RESP_MKEX_PRFL_SIZE GENMASK_ULL(63, 9)
151 #define RESP_MKEX_PRFL_ADDR GENMASK_ULL(63, 9)
156 #define RESP_FWD_BASE GENMASK_ULL(56, 9)
177 #define RESP_LINKSTAT_UP GENMASK_ULL(9, 9)
178 #define RESP_LINKSTAT_FDUPLEX GENMASK_ULL(1
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H A Dnpc.h310 #define NPC_PARSE_NIBBLE GENMASK_ULL(30, 0)
313 #define NPC_PARSE_NIBBLE_CHAN GENMASK_ULL(2, 0)
315 #define NPC_PARSE_NIBBLE_ERRCODE GENMASK_ULL(5, 4)
317 #define NPC_PARSE_NIBBLE_LA_FLAGS GENMASK_ULL(8, 7)
319 #define NPC_PARSE_NIBBLE_LB_FLAGS GENMASK_ULL(11, 10)
321 #define NPC_PARSE_NIBBLE_LC_FLAGS GENMASK_ULL(14, 13)
323 #define NPC_PARSE_NIBBLE_LD_FLAGS GENMASK_ULL(17, 16)
325 #define NPC_PARSE_NIBBLE_LE_FLAGS GENMASK_ULL(20, 19)
327 #define NPC_PARSE_NIBBLE_LF_FLAGS GENMASK_ULL(23, 22)
329 #define NPC_PARSE_NIBBLE_LG_FLAGS GENMASK_ULL(2
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/kernel/linux/linux-6.6/tools/perf/util/arm-spe-decoder/
H A Darm-spe-pkt-decoder.h44 #define SPE_HEADER0_MASK1 (GENMASK_ULL(7, 6) | GENMASK_ULL(3, 0))
48 #define SPE_HEADER0_MASK2 GENMASK_ULL(7, 2)
54 #define SPE_HEADER0_MASK3 GENMASK_ULL(7, 3)
59 #define SPE_HDR_SHORT_INDEX(h) ((h) & GENMASK_ULL(2, 0))
60 #define SPE_HDR_EXTENDED_INDEX(h0, h1) (((h0) & GENMASK_ULL(1, 0)) << 3 | \
72 #define SPE_ADDR_PKT_ADDR_GET_BYTES_0_6(v) ((v) & GENMASK_ULL(55, 0))
73 #define SPE_ADDR_PKT_ADDR_GET_BYTE_6(v) (((v) & GENMASK_ULL(55, 48)) >> 48)
76 #define SPE_ADDR_PKT_GET_EL(v) (((v) & GENMASK_ULL(62, 61)) >> 61)
78 #define SPE_ADDR_PKT_GET_PAT(v) (((v) & GENMASK_ULL(5
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/kernel/linux/linux-6.6/drivers/fpga/
H A Ddfl.h71 #define DFH_ID GENMASK_ULL(11, 0) /* Feature ID */
74 #define DFH_REVISION GENMASK_ULL(15, 12) /* Feature revision */
75 #define DFH_NEXT_HDR_OFST GENMASK_ULL(39, 16) /* Offset to next DFH */
77 #define DFH_VERSION GENMASK_ULL(59, 52) /* DFH version */
78 #define DFH_TYPE GENMASK_ULL(63, 60) /* Feature type */
99 #define DFHv1_CSR_ADDR_MASK GENMASK_ULL(63, 1) /* 63:1 of CSR address */
102 #define DFHv1_CSR_SIZE_GRP_INSTANCE_ID GENMASK_ULL(15, 0) /* Enumeration instantiated IP */
103 #define DFHv1_CSR_SIZE_GRP_GROUPING_ID GENMASK_ULL(30, 16) /* Group Features/interfaces */
105 #define DFHv1_CSR_SIZE_GRP_SIZE GENMASK_ULL(63, 32) /* Size of CSR Block in bytes */
108 #define DFHv1_PARAM_HDR_ID GENMASK_ULL(1
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/kernel/linux/linux-6.6/drivers/infiniband/hw/erdma/
H A Derdma_hw.h90 #define ERDMA_CQDB_IDX_MASK GENMASK_ULL(63, 56)
91 #define ERDMA_CQDB_CQN_MASK GENMASK_ULL(55, 32)
94 #define ERDMA_CQDB_CMDSN_MASK GENMASK_ULL(29, 28)
95 #define ERDMA_CQDB_CI_MASK GENMASK_ULL(23, 0)
98 #define ERDMA_EQDB_CI_MASK GENMASK_ULL(23, 0)
155 #define ERDMA_CMD_HDR_WQEBB_CNT_MASK GENMASK_ULL(54, 52)
156 #define ERDMA_CMD_HDR_CONTEXT_COOKIE_MASK GENMASK_ULL(47, 32)
157 #define ERDMA_CMD_HDR_SUB_MOD_MASK GENMASK_ULL(25, 24)
158 #define ERDMA_CMD_HDR_OPCODE_MASK GENMASK_ULL(23, 16)
159 #define ERDMA_CMD_HDR_WQEBB_INDEX_MASK GENMASK_ULL(1
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/kernel/linux/linux-6.6/drivers/iommu/intel/
H A Dcap_audit.h18 #define CAP_MAMV_MASK GENMASK_ULL(53, 48)
19 #define CAP_NFR_MASK GENMASK_ULL(47, 40)
21 #define CAP_SLLPS_MASK GENMASK_ULL(37, 34)
22 #define CAP_FRO_MASK GENMASK_ULL(33, 24)
24 #define CAP_MGAW_MASK GENMASK_ULL(21, 16)
25 #define CAP_SAGAW_MASK GENMASK_ULL(12, 8)
31 #define CAP_NDOMS_MASK GENMASK_ULL(2, 0)
46 #define ECAP_PSS_MASK GENMASK_ULL(39, 35)
54 #define ECAP_MHMV_MASK GENMASK_ULL(23, 20)
55 #define ECAP_IRO_MASK GENMASK_ULL(1
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/kernel/linux/linux-5.10/lib/
H A Dtest_bits.c29 KUNIT_EXPECT_EQ(test, 1ull, GENMASK_ULL(0, 0)); in genmask_ull_test()
30 KUNIT_EXPECT_EQ(test, 3ull, GENMASK_ULL(1, 0)); in genmask_ull_test()
31 KUNIT_EXPECT_EQ(test, 0x000000ffffe00000ull, GENMASK_ULL(39, 21)); in genmask_ull_test()
32 KUNIT_EXPECT_EQ(test, 0xffffffffffffffffull, GENMASK_ULL(63, 0)); in genmask_ull_test()
36 GENMASK_ULL(0, 1); in genmask_ull_test()
37 GENMASK_ULL(0, 10); in genmask_ull_test()
38 GENMASK_ULL(9, 10); in genmask_ull_test()
/kernel/linux/linux-6.6/lib/
H A Dtest_bits.c29 KUNIT_EXPECT_EQ(test, 1ull, GENMASK_ULL(0, 0)); in genmask_ull_test()
30 KUNIT_EXPECT_EQ(test, 3ull, GENMASK_ULL(1, 0)); in genmask_ull_test()
31 KUNIT_EXPECT_EQ(test, 0x000000ffffe00000ull, GENMASK_ULL(39, 21)); in genmask_ull_test()
32 KUNIT_EXPECT_EQ(test, 0xffffffffffffffffull, GENMASK_ULL(63, 0)); in genmask_ull_test()
36 GENMASK_ULL(0, 1); in genmask_ull_test()
37 GENMASK_ULL(0, 10); in genmask_ull_test()
38 GENMASK_ULL(9, 10); in genmask_ull_test()
/kernel/linux/linux-5.10/drivers/fpga/
H A Ddfl.h70 #define DFH_ID GENMASK_ULL(11, 0) /* Feature ID */
73 #define DFH_REVISION GENMASK_ULL(15, 12) /* Feature revision */
74 #define DFH_NEXT_HDR_OFST GENMASK_ULL(39, 16) /* Offset to next DFH */
76 #define DFH_TYPE GENMASK_ULL(63, 60) /* Feature type */
82 #define NEXT_AFU_NEXT_DFH_OFST GENMASK_ULL(23, 0) /* Offset to next AFU */
95 #define FME_CAP_FABRIC_VERID GENMASK_ULL(7, 0) /* Fabric version ID */
101 #define FME_CAP_NUM_PORTS GENMASK_ULL(19, 17) /* Number of ports */
102 #define FME_CAP_ADDR_WIDTH GENMASK_ULL(29, 24) /* Address bus width */
103 #define FME_CAP_CACHE_SIZE GENMASK_ULL(43, 32) /* cache size in KB */
104 #define FME_CAP_CACHE_ASSOC GENMASK_ULL(4
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/kernel/linux/linux-5.10/include/linux/irqchip/
H A Darm-gic-v3.h171 #define GIC_ENCODE_SZ(n, w) (((unsigned long)(n) - 1) & GENMASK_ULL(((w) - 1), 0))
197 #define GICR_PROPBASER_ADDRESS(x) ((x) & GENMASK_ULL(51, 12))
198 #define GICR_PENDBASER_ADDRESS(x) ((x) & GENMASK_ULL(51, 16))
246 #define GICR_TYPER_COMMON_LPI_AFF GENMASK_ULL(25, 24)
247 #define GICR_TYPER_AFFINITY GENMASK_ULL(63, 32)
249 #define GICR_INVLPIR_INTID GENMASK_ULL(31, 0)
250 #define GICR_INVLPIR_VPEID GENMASK_ULL(47, 32)
251 #define GICR_INVLPIR_V GENMASK_ULL(63, 63)
298 #define GICR_VPROPBASER_4_1_ENTRY_SIZE GENMASK_ULL(61, 59)
300 #define GICR_VPROPBASER_4_1_PAGE_SIZE GENMASK_ULL(5
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/kernel/linux/linux-6.6/include/linux/irqchip/
H A Darm-gic-v3.h173 #define GIC_ENCODE_SZ(n, w) (((unsigned long)(n) - 1) & GENMASK_ULL(((w) - 1), 0))
199 #define GICR_PROPBASER_ADDRESS(x) ((x) & GENMASK_ULL(51, 12))
200 #define GICR_PENDBASER_ADDRESS(x) ((x) & GENMASK_ULL(51, 16))
248 #define GICR_TYPER_COMMON_LPI_AFF GENMASK_ULL(25, 24)
249 #define GICR_TYPER_AFFINITY GENMASK_ULL(63, 32)
251 #define GICR_INVLPIR_INTID GENMASK_ULL(31, 0)
252 #define GICR_INVLPIR_VPEID GENMASK_ULL(47, 32)
253 #define GICR_INVLPIR_V GENMASK_ULL(63, 63)
300 #define GICR_VPROPBASER_4_1_ENTRY_SIZE GENMASK_ULL(61, 59)
302 #define GICR_VPROPBASER_4_1_PAGE_SIZE GENMASK_ULL(5
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/kernel/linux/linux-5.10/arch/arm64/kvm/vgic/
H A Dvgic.h72 #define KVM_ITS_CTE_ICID_MASK GENMASK_ULL(15, 0)
75 #define KVM_ITS_ITE_PINTID_MASK GENMASK_ULL(47, 16)
76 #define KVM_ITS_ITE_ICID_MASK GENMASK_ULL(15, 0)
80 #define KVM_ITS_DTE_NEXT_MASK GENMASK_ULL(62, 49)
82 #define KVM_ITS_DTE_ITTADDR_MASK GENMASK_ULL(48, 5)
83 #define KVM_ITS_DTE_SIZE_MASK GENMASK_ULL(4, 0)
86 #define KVM_ITS_L1E_ADDR_MASK GENMASK_ULL(51, 16)
88 #define KVM_VGIC_V3_RDIST_INDEX_MASK GENMASK_ULL(11, 0)
89 #define KVM_VGIC_V3_RDIST_FLAGS_MASK GENMASK_ULL(15, 12)
91 #define KVM_VGIC_V3_RDIST_BASE_MASK GENMASK_ULL(5
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/kernel/linux/linux-6.6/drivers/accel/ivpu/
H A Divpu_mmu.c96 #define IVPU_MMU_EVT_OP_MASK GENMASK_ULL(7, 0)
97 #define IVPU_MMU_EVT_SSID_MASK GENMASK_ULL(31, 12)
100 #define IVPU_MMU_Q_BASE_ADDR_MASK GENMASK_ULL(51, 5)
102 #define IVPU_MMU_STRTAB_BASE_ADDR_MASK GENMASK_ULL(51, 6)
126 #define IVPU_MMU_CMDQ_OP GENMASK_ULL(7, 0)
128 #define IVPU_MMU_CD_0_TCR_T0SZ GENMASK_ULL(5, 0)
129 #define IVPU_MMU_CD_0_TCR_TG0 GENMASK_ULL(7, 6)
130 #define IVPU_MMU_CD_0_TCR_IRGN0 GENMASK_ULL(9, 8)
131 #define IVPU_MMU_CD_0_TCR_ORGN0 GENMASK_ULL(11, 10)
132 #define IVPU_MMU_CD_0_TCR_SH0 GENMASK_ULL(1
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