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Searched refs:FR_PLL_DIV0 (Results 1 - 2 of 2) sorted by relevance

/kernel/linux/linux-6.6/drivers/net/phy/
H A Dmeson-gxl.c38 #define FR_PLL_DIV0 0x1c macro
128 ret = meson_gxl_write_reg(phydev, BANK_BIST, FR_PLL_DIV0, 0xaaaa); in meson_gxl_config_init()
/kernel/linux/linux-5.10/drivers/net/phy/
H A Dmeson-gxl.c45 #define FR_PLL_DIV0 0x1c macro
135 ret = meson_gxl_write_reg(phydev, BANK_BIST, FR_PLL_DIV0, 0xaaaa); in meson_gxl_config_init()

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