ENABLE_PCLK_AUD (reference) in projects: kernel - OpenGrok search results

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Searched refs:ENABLE_PCLK_AUD (Results 1 - 4 of 4) sorted by relevance

/kernel/linux/linux-5.10/drivers/clk/samsung/
H A D	clk-exynos7.c	1234 #define ENABLE_PCLK_AUD 0x0900 macro 1248 ENABLE_PCLK_AUD, 1279 GATE(0, "pclk_dbg_aud", "dout_aud_pclk_dbg", ENABLE_PCLK_AUD, 19, 0, 0), 1280 GATE(0, "pclk_gpio_aud", "dout_aclk_aud", ENABLE_PCLK_AUD, 20, 0, 0), 1281 GATE(0, "pclk_wdt1", "dout_aclk_aud", ENABLE_PCLK_AUD, 22, 0, 0), 1282 GATE(0, "pclk_wdt0", "dout_aclk_aud", ENABLE_PCLK_AUD, 23, 0, 0), 1283 GATE(0, "pclk_slimbus", "dout_aclk_aud", ENABLE_PCLK_AUD, 24, 0, 0), 1284 GATE(0, "pclk_uart", "dout_aclk_aud", ENABLE_PCLK_AUD, 25, 0, 0), 1286 ENABLE_PCLK_AUD, 26, CLK_SET_RATE_PARENT, 0), 1288 ENABLE_PCLK_AUD, 2 [all...]
H A D	clk-exynos5433.c	`2911 #define ENABLE_PCLK_AUD 0x0900 macro 2925 ENABLE_PCLK_AUD, 2998 /* ENABLE_PCLK_AUD */ 2999 GATE(CLK_PCLK_WDT1, "pclk_wdt1", "div_aclk_aud", ENABLE_PCLK_AUD, 3001 GATE(CLK_PCLK_WDT0, "pclk_wdt0", "div_aclk_aud", ENABLE_PCLK_AUD, 3003 GATE(CLK_PCLK_SFR1, "pclk_sfr1", "div_aclk_aud", ENABLE_PCLK_AUD, 3006 ENABLE_PCLK_AUD, 10, 0, 0), 3008 ENABLE_PCLK_AUD, 9, CLK_IGNORE_UNUSED, 0), 3010 ENABLE_PCLK_AUD, 8, CLK_IGNORE_UNUSED, 0), 3012 ENABLE_PCLK_AUD, [all...]`
/kernel/linux/linux-6.6/drivers/clk/samsung/
H A D	clk-exynos7.c	1234 #define ENABLE_PCLK_AUD 0x0900 macro 1248 ENABLE_PCLK_AUD, 1279 GATE(0, "pclk_dbg_aud", "dout_aud_pclk_dbg", ENABLE_PCLK_AUD, 19, 0, 0), 1280 GATE(0, "pclk_gpio_aud", "dout_aclk_aud", ENABLE_PCLK_AUD, 20, 0, 0), 1281 GATE(0, "pclk_wdt1", "dout_aclk_aud", ENABLE_PCLK_AUD, 22, 0, 0), 1282 GATE(0, "pclk_wdt0", "dout_aclk_aud", ENABLE_PCLK_AUD, 23, 0, 0), 1283 GATE(0, "pclk_slimbus", "dout_aclk_aud", ENABLE_PCLK_AUD, 24, 0, 0), 1284 GATE(0, "pclk_uart", "dout_aclk_aud", ENABLE_PCLK_AUD, 25, 0, 0), 1286 ENABLE_PCLK_AUD, 26, CLK_SET_RATE_PARENT, 0), 1288 ENABLE_PCLK_AUD, 2 [all...]
H A D	clk-exynos5433.c	`2934 #define ENABLE_PCLK_AUD 0x0900 macro 2948 ENABLE_PCLK_AUD, 3021 /* ENABLE_PCLK_AUD */ 3022 GATE(CLK_PCLK_WDT1, "pclk_wdt1", "div_aclk_aud", ENABLE_PCLK_AUD, 3024 GATE(CLK_PCLK_WDT0, "pclk_wdt0", "div_aclk_aud", ENABLE_PCLK_AUD, 3026 GATE(CLK_PCLK_SFR1, "pclk_sfr1", "div_aclk_aud", ENABLE_PCLK_AUD, 3029 ENABLE_PCLK_AUD, 10, 0, 0), 3031 ENABLE_PCLK_AUD, 9, CLK_IGNORE_UNUSED, 0), 3033 ENABLE_PCLK_AUD, 8, CLK_IGNORE_UNUSED, 0), 3035 ENABLE_PCLK_AUD, [all...]`

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