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Searched refs:ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE (Results 1 - 18 of 18) sorted by relevance

/kernel/linux/linux-5.10/drivers/gpu/drm/radeon/
H A Dni.c1297 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE | in cayman_pcie_gart_enable()
1376 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE | in cayman_pcie_gart_disable()
H A Dnid.h108 #define ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE (1 << 10) macro
H A Dcikd.h493 #define ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE (1 << 10) macro
H A Dsid.h375 #define ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE (1 << 10) macro
H A Dsi.c4312 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE | in si_pcie_gart_enable()
4398 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE | in si_pcie_gart_disable()
H A Dcik.c5452 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE | in cik_pcie_gart_enable()
5569 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE | in cik_pcie_gart_disable()
/kernel/linux/linux-6.6/drivers/gpu/drm/radeon/
H A Dni.c1284 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE | in cayman_pcie_gart_enable()
1363 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE | in cayman_pcie_gart_disable()
H A Dnid.h108 #define ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE (1 << 10) macro
H A Dcikd.h493 #define ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE (1 << 10) macro
H A Dsid.h375 #define ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE (1 << 10) macro
H A Dsi.c4307 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE | in si_pcie_gart_enable()
4393 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE | in si_pcie_gart_disable()
H A Dcik.c5442 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE | in cik_pcie_gart_enable()
5559 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE | in cik_pcie_gart_disable()
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/amdgpu/
H A Dgmc_v7_0.c637 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1); in gmc_v7_0_gart_enable()
H A Dgmc_v8_0.c870 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1); in gmc_v8_0_gart_enable()
H A Dsid.h376 #define ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE (1 << 10) macro
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/amdgpu/
H A Dgmc_v7_0.c631 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1); in gmc_v7_0_gart_enable()
H A Dgmc_v8_0.c846 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1); in gmc_v8_0_gart_enable()
H A Dsid.h376 #define ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE (1 << 10) macro

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