Searched refs:ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE (Results 1 - 18 of 18) sorted by relevance
/kernel/linux/linux-5.10/drivers/gpu/drm/radeon/ |
H A D | ni.c | 1297 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE | in cayman_pcie_gart_enable() 1376 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE | in cayman_pcie_gart_disable()
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H A D | nid.h | 108 #define ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE (1 << 10) macro
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H A D | cikd.h | 493 #define ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE (1 << 10) macro
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H A D | sid.h | 375 #define ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE (1 << 10) macro
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H A D | si.c | 4312 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE | in si_pcie_gart_enable() 4398 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE | in si_pcie_gart_disable()
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H A D | cik.c | 5452 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE | in cik_pcie_gart_enable() 5569 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE | in cik_pcie_gart_disable()
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/kernel/linux/linux-6.6/drivers/gpu/drm/radeon/ |
H A D | ni.c | 1284 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE | in cayman_pcie_gart_enable() 1363 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE | in cayman_pcie_gart_disable()
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H A D | nid.h | 108 #define ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE (1 << 10) macro
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H A D | cikd.h | 493 #define ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE (1 << 10) macro
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H A D | sid.h | 375 #define ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE (1 << 10) macro
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H A D | si.c | 4307 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE | in si_pcie_gart_enable() 4393 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE | in si_pcie_gart_disable()
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H A D | cik.c | 5442 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE | in cik_pcie_gart_enable() 5559 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE | in cik_pcie_gart_disable()
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/kernel/linux/linux-5.10/drivers/gpu/drm/amd/amdgpu/ |
H A D | gmc_v7_0.c | 637 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1); in gmc_v7_0_gart_enable()
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H A D | gmc_v8_0.c | 870 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1); in gmc_v8_0_gart_enable()
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H A D | sid.h | 376 #define ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE (1 << 10) macro
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/kernel/linux/linux-6.6/drivers/gpu/drm/amd/amdgpu/ |
H A D | gmc_v7_0.c | 631 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1); in gmc_v7_0_gart_enable()
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H A D | gmc_v8_0.c | 846 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1); in gmc_v8_0_gart_enable()
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H A D | sid.h | 376 #define ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE (1 << 10) macro
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