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Searched refs:EMC_ZCAL_INTERVAL (Results 1 - 12 of 12) sorted by relevance

/kernel/linux/linux-5.10/arch/arm/mach-tegra/
H A Dsleep-tegra30.S31 #define EMC_ZCAL_INTERVAL 0x2e0 define
523 ldr r1, [r5, #0x4] @ restore EMC_ZCAL_INTERVAL
524 str r1, [r0, #EMC_ZCAL_INTERVAL]
548 .word TEGRA_EMC_BASE + EMC_ZCAL_INTERVAL @0x4
559 .word TEGRA_EMC0_BASE + EMC_ZCAL_INTERVAL @0x4
567 .word TEGRA_EMC1_BASE + EMC_ZCAL_INTERVAL @0x24
575 .word TEGRA124_EMC_BASE + EMC_ZCAL_INTERVAL @0x4
773 str r1, [r0, #EMC_ZCAL_INTERVAL]
/kernel/linux/linux-6.6/arch/arm/mach-tegra/
H A Dsleep-tegra30.S31 #define EMC_ZCAL_INTERVAL 0x2e0 define
568 ldr r1, [r5, #0x4] @ restore EMC_ZCAL_INTERVAL
569 str r1, [r0, #EMC_ZCAL_INTERVAL]
593 .word TEGRA_EMC_BASE + EMC_ZCAL_INTERVAL @0x4
604 .word TEGRA_EMC0_BASE + EMC_ZCAL_INTERVAL @0x4
612 .word TEGRA_EMC1_BASE + EMC_ZCAL_INTERVAL @0x24
620 .word TEGRA124_EMC_BASE + EMC_ZCAL_INTERVAL @0x4
829 str r1, [r0, #EMC_ZCAL_INTERVAL]
/kernel/linux/linux-5.10/drivers/memory/tegra/
H A Dtegra210-emc-cc-r21021.c1048 } else if (offset == EMC_ZCAL_INTERVAL && opt_zcal_en_cc) { in tegra210_emc_r21021_set_clock()
1049 value = 0; /* EMC_ZCAL_INTERVAL reset value. */ in tegra210_emc_r21021_set_clock()
1245 emc_writel(emc, 0, EMC_ZCAL_INTERVAL); in tegra210_emc_r21021_set_clock()
1252 emc_writel(emc, 0, EMC_ZCAL_INTERVAL); in tegra210_emc_r21021_set_clock()
1607 EMC_ZCAL_INTERVAL, 0); in tegra210_emc_r21021_set_clock()
1683 EMC_ZCAL_INTERVAL); in tegra210_emc_r21021_set_clock()
H A Dtegra30-emc.c93 #define EMC_ZCAL_INTERVAL 0x2e0 macro
301 [80] = EMC_ZCAL_INTERVAL,
525 if (timing->data[80] && !readl_relaxed(emc->regs + EMC_ZCAL_INTERVAL)) in emc_prepare_timing_change()
H A Dtegra124-emc.c140 #define EMC_ZCAL_INTERVAL 0x2e0 macro
671 writel(timing->emc_zcal_interval, emc->regs + EMC_ZCAL_INTERVAL); in tegra_emc_prepare_timing_change()
H A Dtegra210-emc.h167 #define EMC_ZCAL_INTERVAL 0x2e0 macro
H A Dtegra210-emc-core.c236 EMC_ZCAL_INTERVAL,
/kernel/linux/linux-6.6/drivers/memory/tegra/
H A Dtegra210-emc-cc-r21021.c1048 } else if (offset == EMC_ZCAL_INTERVAL && opt_zcal_en_cc) { in tegra210_emc_r21021_set_clock()
1049 value = 0; /* EMC_ZCAL_INTERVAL reset value. */ in tegra210_emc_r21021_set_clock()
1245 emc_writel(emc, 0, EMC_ZCAL_INTERVAL); in tegra210_emc_r21021_set_clock()
1252 emc_writel(emc, 0, EMC_ZCAL_INTERVAL); in tegra210_emc_r21021_set_clock()
1607 EMC_ZCAL_INTERVAL, 0); in tegra210_emc_r21021_set_clock()
1683 EMC_ZCAL_INTERVAL); in tegra210_emc_r21021_set_clock()
H A Dtegra124-emc.c147 #define EMC_ZCAL_INTERVAL 0x2e0 macro
701 writel(timing->emc_zcal_interval, emc->regs + EMC_ZCAL_INTERVAL); in tegra_emc_prepare_timing_change()
H A Dtegra30-emc.c104 #define EMC_ZCAL_INTERVAL 0x2e0 macro
319 [80] = EMC_ZCAL_INTERVAL,
566 if (timing->data[80] && !readl_relaxed(emc->regs + EMC_ZCAL_INTERVAL)) in emc_prepare_timing_change()
H A Dtegra210-emc.h167 #define EMC_ZCAL_INTERVAL 0x2e0 macro
H A Dtegra210-emc-core.c236 EMC_ZCAL_INTERVAL,

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