Home
last modified time | relevance | path

Searched refs:EMC_CFG (Results 1 - 14 of 14) sorted by relevance

/kernel/linux/linux-5.10/arch/arm/mach-tegra/
H A Dsleep-tegra30.S18 #define EMC_CFG 0xc define
457 ldr r1, [r0, #EMC_CFG]
459 str r1, [r0, #EMC_CFG]
525 ldr r1, [r5, #0x0] @ restore EMC_CFG
526 str r1, [r0, #EMC_CFG]
547 .word TEGRA_EMC_BASE + EMC_CFG @0x0
558 .word TEGRA_EMC0_BASE + EMC_CFG @0x0
566 .word TEGRA_EMC1_BASE + EMC_CFG @0x20
574 .word TEGRA124_EMC_BASE + EMC_CFG @0x0
775 ldr r1, [r0, #EMC_CFG]
[all...]
H A Dsleep-tegra20.S23 #define EMC_CFG 0xc define
213 ldr r1, [r0, #EMC_CFG]
215 str r1, [r0, #EMC_CFG]
/kernel/linux/linux-6.6/arch/arm/mach-tegra/
H A Dsleep-tegra30.S18 #define EMC_CFG 0xc define
502 ldr r1, [r0, #EMC_CFG]
504 str r1, [r0, #EMC_CFG]
570 ldr r1, [r5, #0x0] @ restore EMC_CFG
571 str r1, [r0, #EMC_CFG]
592 .word TEGRA_EMC_BASE + EMC_CFG @0x0
603 .word TEGRA_EMC0_BASE + EMC_CFG @0x0
611 .word TEGRA_EMC1_BASE + EMC_CFG @0x20
619 .word TEGRA124_EMC_BASE + EMC_CFG @0x0
831 ldr r1, [r0, #EMC_CFG]
[all...]
H A Dsleep-tegra20.S23 #define EMC_CFG 0xc define
238 ldr r1, [r0, #EMC_CFG]
240 str r1, [r0, #EMC_CFG]
/kernel/linux/linux-5.10/drivers/memory/tegra/
H A Dtegra124-emc.c32 #define EMC_CFG 0xc macro
590 val = readl(emc->regs + EMC_CFG); in tegra_emc_prepare_timing_change()
593 writel(val, emc->regs + EMC_CFG); in tegra_emc_prepare_timing_change()
676 emc_ccfifo_writel(emc, val, EMC_CFG); in tegra_emc_prepare_timing_change()
813 writel(timing->emc_cfg, emc->regs + EMC_CFG); in tegra_emc_complete_timing_change()
859 timing->emc_cfg = readl(emc->regs + EMC_CFG); in emc_read_current_timing()
H A Dtegra30-emc.c34 #define EMC_CFG 0x00c macro
513 emc->emc_cfg = readl_relaxed(emc->regs + EMC_CFG); in emc_prepare_timing_change()
538 writel_relaxed(emc->emc_cfg, emc->regs + EMC_CFG); in emc_prepare_timing_change()
651 emc->regs + EMC_CFG); in emc_prepare_timing_change()
685 writel_relaxed(emc->emc_cfg, emc->regs + EMC_CFG); in emc_prepare_timing_change()
780 writel_relaxed(emc->emc_cfg, emc->regs + EMC_CFG); in emc_complete_timing_change()
H A Dtegra210-emc-cc-r21021.c501 emc_cfg_o = emc_readl(emc, EMC_CFG); in tegra210_emc_r21021_periodic_compensation()
510 emc_writel(emc, emc_cfg, EMC_CFG); in tegra210_emc_r21021_periodic_compensation()
565 emc_writel(emc, emc_cfg_o, EMC_CFG); in tegra210_emc_r21021_periodic_compensation()
648 emc_readl(emc, EMC_CFG); in tegra210_emc_r21021_set_clock()
720 emc_writel(emc, emc_cfg, EMC_CFG); in tegra210_emc_r21021_set_clock()
752 emc_writel(emc, emc_cfg, EMC_CFG); in tegra210_emc_r21021_set_clock()
859 * Update EMC_CFG. (??) in tegra210_emc_r21021_set_clock()
1025 if (offset == EMC_CFG) { in tegra210_emc_r21021_set_clock()
1612 EMC_CFG, 0); in tegra210_emc_r21021_set_clock()
1703 * Restore EMC_CFG, FDP in tegra210_emc_r21021_set_clock()
[all...]
H A Dtegra210-emc.h26 #define EMC_CFG 0xc macro
H A Dtegra210-emc-core.c245 EMC_CFG,
/kernel/linux/linux-6.6/drivers/memory/tegra/
H A Dtegra124-emc.c39 #define EMC_CFG 0xc macro
620 val = readl(emc->regs + EMC_CFG); in tegra_emc_prepare_timing_change()
623 writel(val, emc->regs + EMC_CFG); in tegra_emc_prepare_timing_change()
706 emc_ccfifo_writel(emc, val, EMC_CFG); in tegra_emc_prepare_timing_change()
843 writel(timing->emc_cfg, emc->regs + EMC_CFG); in tegra_emc_complete_timing_change()
889 timing->emc_cfg = readl(emc->regs + EMC_CFG); in emc_read_current_timing()
H A Dtegra210-emc-cc-r21021.c501 emc_cfg_o = emc_readl(emc, EMC_CFG); in tegra210_emc_r21021_periodic_compensation()
510 emc_writel(emc, emc_cfg, EMC_CFG); in tegra210_emc_r21021_periodic_compensation()
565 emc_writel(emc, emc_cfg_o, EMC_CFG); in tegra210_emc_r21021_periodic_compensation()
648 emc_readl(emc, EMC_CFG); in tegra210_emc_r21021_set_clock()
720 emc_writel(emc, emc_cfg, EMC_CFG); in tegra210_emc_r21021_set_clock()
752 emc_writel(emc, emc_cfg, EMC_CFG); in tegra210_emc_r21021_set_clock()
859 * Update EMC_CFG. (??) in tegra210_emc_r21021_set_clock()
1025 if (offset == EMC_CFG) { in tegra210_emc_r21021_set_clock()
1612 EMC_CFG, 0); in tegra210_emc_r21021_set_clock()
1703 * Restore EMC_CFG, FDP in tegra210_emc_r21021_set_clock()
[all...]
H A Dtegra30-emc.c44 #define EMC_CFG 0x00c macro
554 emc->emc_cfg = readl_relaxed(emc->regs + EMC_CFG); in emc_prepare_timing_change()
579 writel_relaxed(emc->emc_cfg, emc->regs + EMC_CFG); in emc_prepare_timing_change()
692 emc->regs + EMC_CFG); in emc_prepare_timing_change()
726 writel_relaxed(emc->emc_cfg, emc->regs + EMC_CFG); in emc_prepare_timing_change()
821 writel_relaxed(emc->emc_cfg, emc->regs + EMC_CFG); in emc_complete_timing_change()
H A Dtegra210-emc.h26 #define EMC_CFG 0xc macro
H A Dtegra210-emc-core.c245 EMC_CFG,

Completed in 25 milliseconds