| /kernel/linux/linux-6.6/drivers/gpu/drm/i915/display/ |
| H A D | i9xx_plane.c | 495 intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane), in i9xx_plane_update_arm()
538 intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane), 0); in i9xx_plane_disable_arm()
559 intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane), in g4x_primary_async_flip()
1026 base = intel_de_read(dev_priv, DSPSURF(i9xx_plane)) & DISP_ADDR_MASK; in i9xx_get_initial_plane_config()
1034 base = intel_de_read(dev_priv, DSPSURF(i9xx_plane)) & DISP_ADDR_MASK; in i9xx_get_initial_plane_config()
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| H A D | intel_fbc.c | 362 intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane), in i965_fbc_nuke()
363 intel_de_read_fw(dev_priv, DSPSURF(i9xx_plane))); in i965_fbc_nuke()
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| /kernel/linux/linux-6.6/drivers/gpu/drm/i915/ |
| H A D | intel_clock_gating.c | 147 intel_uncore_rmw(&dev_priv->uncore, DSPSURF(pipe), 0, 0); in g4x_disable_trickle_feed()
148 intel_uncore_posting_read(&dev_priv->uncore, DSPSURF(pipe)); in g4x_disable_trickle_feed()
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| H A D | intel_gvt_mmio_table.c | 165 MMIO_D(DSPSURF(PIPE_A)); in iterate_generic_mmio()
174 MMIO_D(DSPSURF(PIPE_B)); in iterate_generic_mmio()
183 MMIO_D(DSPSURF(PIPE_C)); in iterate_generic_mmio()
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| H A D | i915_reg.h | 3163 #define DSPSURF(plane) _MMIO_PIPE2(plane, _DSPASURF) macro
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| /kernel/linux/linux-5.10/drivers/gpu/drm/i915/gvt/ |
| H A D | fb_decoder.c | 247 plane->base = vgpu_vreg_t(vgpu, DSPSURF(pipe)) & I915_GTT_PAGE_MASK; in intel_vgpu_decode_primary_plane()
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| H A D | handlers.c | 755 calc_index(offset, _DSPASURF, _DSPBSURF, 0, DSPSURF(PIPE_C))
2090 MMIO_DH(DSPSURF(PIPE_A), D_ALL, NULL, pri_surf_mmio_write); in init_generic_mmio_info()
2101 MMIO_DH(DSPSURF(PIPE_B), D_ALL, NULL, pri_surf_mmio_write); in init_generic_mmio_info()
2112 MMIO_DH(DSPSURF(PIPE_C), D_ALL, NULL, pri_surf_mmio_write); in init_generic_mmio_info()
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| H A D | cmd_parser.c | 1281 info->surf_reg = DSPSURF(info->pipe); in gen8_decode_mi_display_flip()
1347 info->surf_reg = DSPSURF(info->pipe); in skl_decode_mi_display_flip()
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| /kernel/linux/linux-6.6/drivers/gpu/drm/i915/gvt/ |
| H A D | fb_decoder.c | 248 plane->base = vgpu_vreg_t(vgpu, DSPSURF(pipe)) & I915_GTT_PAGE_MASK; in intel_vgpu_decode_primary_plane()
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| H A D | handlers.c | 1006 calc_index(offset, _DSPASURF, _DSPBSURF, 0, DSPSURF(PIPE_C))
2274 MMIO_DH(DSPSURF(PIPE_A), D_ALL, NULL, pri_surf_mmio_write); in init_generic_mmio_info()
2277 MMIO_DH(DSPSURF(PIPE_B), D_ALL, NULL, pri_surf_mmio_write); in init_generic_mmio_info()
2280 MMIO_DH(DSPSURF(PIPE_C), D_ALL, NULL, pri_surf_mmio_write); in init_generic_mmio_info()
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| H A D | cmd_parser.c | 1318 info->surf_reg = DSPSURF(info->pipe); in gen8_decode_mi_display_flip()
1384 info->surf_reg = DSPSURF(info->pipe); in skl_decode_mi_display_flip()
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| /kernel/linux/linux-5.10/drivers/gpu/drm/i915/display/ |
| H A D | intel_fbc.c | 207 intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane), in i965_fbc_recompress()
208 intel_de_read_fw(dev_priv, DSPSURF(i9xx_plane))); in i965_fbc_recompress()
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| H A D | intel_display.c | 4483 intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane), in i9xx_update_plane()
4516 intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane), 0); in i9xx_disable_plane()
9353 base = intel_de_read(dev_priv, DSPSURF(i9xx_plane)) & 0xfffff000; in i9xx_get_initial_plane_config()
9361 base = intel_de_read(dev_priv, DSPSURF(i9xx_plane)) & 0xfffff000; in i9xx_get_initial_plane_config()
19052 DSPSURF(i)); in intel_display_capture_error_state()
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| /kernel/linux/linux-5.10/drivers/gpu/drm/i915/ |
| H A D | intel_pm.c | 6882 I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe))); in g4x_disable_trickle_feed()
6883 POSTING_READ(DSPSURF(pipe)); in g4x_disable_trickle_feed()
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| H A D | i915_reg.h | 6534 #define DSPSURF(plane) _MMIO_PIPE2(plane, _DSPASURF) macro
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