DRX_CFG_BASE (reference) in projects: kernel - OpenGrok search results

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Searched refs:DRX_CFG_BASE (Results 1 - 2 of 2) sorted by relevance

/kernel/linux/linux-5.10/drivers/media/dvb-frontends/drx39xyj/
H A D	drx_driver.h	896 #ifndef DRX_CFG_BASE 897 #define DRX_CFG_BASE 0 macro 900 #define DRX_CFG_MPEG_OUTPUT (DRX_CFG_BASE + 0) /* MPEG TS output / 901 #define DRX_CFG_PKTERR (DRX_CFG_BASE + 1) / Packet Error / 902 #define DRX_CFG_SYMCLK_OFFS (DRX_CFG_BASE + 2) / Symbol Clk Offset / 903 #define DRX_CFG_SMA (DRX_CFG_BASE + 3) / Smart Antenna / 904 #define DRX_CFG_PINSAFE (DRX_CFG_BASE + 4) / Pin safe mode / 905 #define DRX_CFG_SUBSTANDARD (DRX_CFG_BASE + 5) / substandard / 906 #define DRX_CFG_AUD_VOLUME (DRX_CFG_BASE + 6) / volume */ 907 #define DRX_CFG_AUD_RDS (DRX_CFG_BASE [all...]
/kernel/linux/linux-6.6/drivers/media/dvb-frontends/drx39xyj/
H A D	drx_driver.h	896 #ifndef DRX_CFG_BASE 897 #define DRX_CFG_BASE 0 macro 900 #define DRX_CFG_MPEG_OUTPUT (DRX_CFG_BASE + 0) /* MPEG TS output / 901 #define DRX_CFG_PKTERR (DRX_CFG_BASE + 1) / Packet Error / 902 #define DRX_CFG_SYMCLK_OFFS (DRX_CFG_BASE + 2) / Symbol Clk Offset / 903 #define DRX_CFG_SMA (DRX_CFG_BASE + 3) / Smart Antenna / 904 #define DRX_CFG_PINSAFE (DRX_CFG_BASE + 4) / Pin safe mode / 905 #define DRX_CFG_SUBSTANDARD (DRX_CFG_BASE + 5) / substandard / 906 #define DRX_CFG_AUD_VOLUME (DRX_CFG_BASE + 6) / volume */ 907 #define DRX_CFG_AUD_RDS (DRX_CFG_BASE [all...]

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