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Searched refs:DPU_MAX_PLANES (Results 1 - 12 of 12) sorted by relevance

/kernel/linux/linux-5.10/drivers/gpu/drm/msm/disp/dpu1/
H A Ddpu_hw_util.h104 int32_t init_phase_x[DPU_MAX_PLANES];
105 int32_t phase_step_x[DPU_MAX_PLANES];
106 int32_t init_phase_y[DPU_MAX_PLANES];
107 int32_t phase_step_y[DPU_MAX_PLANES];
109 u32 preload_x[DPU_MAX_PLANES];
110 u32 preload_y[DPU_MAX_PLANES];
111 u32 src_width[DPU_MAX_PLANES];
112 u32 src_height[DPU_MAX_PLANES];
160 int32_t num_ext_pxls_lr[DPU_MAX_PLANES];
161 int32_t num_ext_pxls_tb[DPU_MAX_PLANES];
[all...]
H A Ddpu_hw_sspp.h104 int init_phase_x[DPU_MAX_PLANES];
105 int phase_step_x[DPU_MAX_PLANES];
106 int init_phase_y[DPU_MAX_PLANES];
107 int phase_step_y[DPU_MAX_PLANES];
114 int num_ext_pxls_left[DPU_MAX_PLANES];
115 int num_ext_pxls_right[DPU_MAX_PLANES];
116 int num_ext_pxls_top[DPU_MAX_PLANES];
117 int num_ext_pxls_btm[DPU_MAX_PLANES];
123 int left_ftch[DPU_MAX_PLANES];
124 int right_ftch[DPU_MAX_PLANES];
[all...]
H A Ddpu_hw_mdss.h29 #ifndef DPU_MAX_PLANES
30 #define DPU_MAX_PLANES 4 macro
357 u8 element[DPU_MAX_PLANES];
358 u8 bits[DPU_MAX_PLANES];
390 uint32_t plane_addr[DPU_MAX_PLANES];
391 uint32_t plane_size[DPU_MAX_PLANES];
392 uint32_t plane_pitch[DPU_MAX_PLANES];
H A Ddpu_formats.c671 for (i = 0; i < DPU_MAX_PLANES; i++) in _dpu_format_get_plane_sizes_ubwc()
738 for (i = 0; i < layout->num_planes && i < DPU_MAX_PLANES; ++i) { in _dpu_format_get_plane_sizes_linear()
743 for (i = 0; i < DPU_MAX_PLANES; i++) in _dpu_format_get_plane_sizes_linear()
898 uint32_t plane_addr[DPU_MAX_PLANES]; in dpu_format_populate_layout()
920 for (i = 0; i < DPU_MAX_PLANES; ++i) in dpu_format_populate_layout()
H A Ddpu_hw_sspp.c372 for (color = 0; color < DPU_MAX_PLANES; color++) { in dpu_hw_sspp_setup_pe_config()
H A Ddpu_plane.c558 for (i = 0; i < DPU_MAX_PLANES; i++) { in _dpu_plane_setup_scaler3()
/kernel/linux/linux-6.6/drivers/gpu/drm/msm/disp/dpu1/
H A Ddpu_hw_sspp.h110 int init_phase_x[DPU_MAX_PLANES];
111 int phase_step_x[DPU_MAX_PLANES];
112 int init_phase_y[DPU_MAX_PLANES];
113 int phase_step_y[DPU_MAX_PLANES];
120 int num_ext_pxls_left[DPU_MAX_PLANES];
121 int num_ext_pxls_right[DPU_MAX_PLANES];
122 int num_ext_pxls_top[DPU_MAX_PLANES];
123 int num_ext_pxls_btm[DPU_MAX_PLANES];
129 int left_ftch[DPU_MAX_PLANES];
130 int right_ftch[DPU_MAX_PLANES];
[all...]
H A Ddpu_hw_util.h113 int32_t init_phase_x[DPU_MAX_PLANES];
114 int32_t phase_step_x[DPU_MAX_PLANES];
115 int32_t init_phase_y[DPU_MAX_PLANES];
116 int32_t phase_step_y[DPU_MAX_PLANES];
118 u32 preload_x[DPU_MAX_PLANES];
119 u32 preload_y[DPU_MAX_PLANES];
120 u32 src_width[DPU_MAX_PLANES];
121 u32 src_height[DPU_MAX_PLANES];
171 int32_t num_ext_pxls_lr[DPU_MAX_PLANES];
172 int32_t num_ext_pxls_tb[DPU_MAX_PLANES];
[all...]
H A Ddpu_hw_mdss.h29 #ifndef DPU_MAX_PLANES
30 #define DPU_MAX_PLANES 4 macro
385 u8 element[DPU_MAX_PLANES];
386 u8 bits[DPU_MAX_PLANES];
418 uint32_t plane_addr[DPU_MAX_PLANES];
419 uint32_t plane_size[DPU_MAX_PLANES];
420 uint32_t plane_pitch[DPU_MAX_PLANES];
H A Ddpu_formats.c705 for (i = 0; i < DPU_MAX_PLANES; i++) in _dpu_format_get_plane_sizes_ubwc()
772 for (i = 0; i < layout->num_planes && i < DPU_MAX_PLANES; ++i) { in _dpu_format_get_plane_sizes_linear()
777 for (i = 0; i < DPU_MAX_PLANES; i++) in _dpu_format_get_plane_sizes_linear()
H A Ddpu_hw_sspp.c342 for (color = 0; color < DPU_MAX_PLANES; color++) { in dpu_hw_sspp_setup_pe_config()
H A Ddpu_plane.c433 for (i = 0; i < DPU_MAX_PLANES; i++) { in _dpu_plane_setup_scaler3()
471 for (i = 0; i < DPU_MAX_PLANES; i++) { in _dpu_plane_setup_pixel_ext()

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