Searched refs:DKL_PLL_DIV0 (Results 1 - 4 of 4) sorted by relevance
| /kernel/linux/linux-6.6/drivers/gpu/drm/i915/display/ |
| H A D | intel_dkl_phy_regs.h | 57 #define DKL_PLL_DIV0(tc_port) _DKL_REG(tc_port, \ macro
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| H A D | intel_dpll_mgr.c | 3502 hw_state->mg_pll_div0 = intel_dkl_phy_read(dev_priv, DKL_PLL_DIV0(tc_port)); in dkl_pll_get_hw_state()
3727 intel_dkl_phy_rmw(dev_priv, DKL_PLL_DIV0(tc_port), val, in dkl_pll_write()
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| /kernel/linux/linux-5.10/drivers/gpu/drm/i915/display/ |
| H A D | intel_dpll_mgr.c | 3782 hw_state->mg_pll_div0 = intel_de_read(dev_priv, DKL_PLL_DIV0(tc_port)); in dkl_pll_get_hw_state()
3990 val = intel_de_read(dev_priv, DKL_PLL_DIV0(tc_port)); in dkl_pll_write()
3996 intel_de_write(dev_priv, DKL_PLL_DIV0(tc_port), val); in dkl_pll_write()
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| /kernel/linux/linux-5.10/drivers/gpu/drm/i915/ |
| H A D | i915_reg.h | 10559 #define DKL_PLL_DIV0(tc_port) _MMIO(_PORT(tc_port, _DKL_PHY1_BASE, \ macro
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