| /kernel/linux/linux-5.10/drivers/clk/samsung/ |
| H A D | clk-exynos5410.c | 38 #define DIV_FSYS1 0x1054c macro
142 DIV(0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4),
143 DIV(0, "div_mmc1", "mout_mmc1", DIV_FSYS1, 16, 4),
147 DIV_FSYS1, 8, 8, CLK_SET_RATE_PARENT, 0),
149 DIV_FSYS1, 24, 8, CLK_SET_RATE_PARENT, 0),
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| H A D | clk-exynos3250.c | 57 #define DIV_FSYS1 0xc544 macro
141 DIV_FSYS1,
383 /* DIV_FSYS1 */
384 DIV_F(CLK_DIV_MMC1_PRE, "div_mmc1_pre", "div_mmc1", DIV_FSYS1, 24, 8,
386 DIV(CLK_DIV_MMC1, "div_mmc1", "mout_mmc1", DIV_FSYS1, 16, 4),
387 DIV_F(CLK_DIV_MMC0_PRE, "div_mmc0_pre", "div_mmc0", DIV_FSYS1, 8, 8,
389 DIV(CLK_DIV_MMC0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4),
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| H A D | clk-exynos5250.c | 65 #define DIV_FSYS1 0x1054c macro
146 DIV_FSYS1,
392 DIV(0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4),
394 DIV_FSYS1, 8, 8, CLK_SET_RATE_PARENT, 0),
395 DIV(0, "div_mmc1", "mout_mmc1", DIV_FSYS1, 16, 4),
397 DIV_FSYS1, 24, 8, CLK_SET_RATE_PARENT, 0),
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| H A D | clk-exynos4.c | 76 #define DIV_FSYS1 0xc544 macro
223 DIV_FSYS1,
625 DIV(0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4),
626 DIV(0, "div_mmc1", "mout_mmc1", DIV_FSYS1, 16, 4),
658 DIV_F(0, "div_mmc_pre0", "div_mmc0", DIV_FSYS1, 8, 8,
660 DIV_F(0, "div_mmc_pre1", "div_mmc1", DIV_FSYS1, 24, 8,
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| H A D | clk-exynos7.c | 989 #define DIV_FSYS1 0x0600 macro
1023 DIV_FSYS1,
1056 DIV_FSYS1, 0, 2),
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| H A D | clk-exynos5420.c | 90 #define DIV_FSYS1 0x1054c macro
216 DIV_FSYS1,
870 DIV(0, "dout_mmc0", "mout_mmc0", DIV_FSYS1, 0, 10),
871 DIV(0, "dout_mmc1", "mout_mmc1", DIV_FSYS1, 10, 10),
872 DIV(0, "dout_mmc2", "mout_mmc2", DIV_FSYS1, 20, 10),
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| /kernel/linux/linux-6.6/drivers/clk/samsung/ |
| H A D | clk-exynos5410.c | 38 #define DIV_FSYS1 0x1054c macro
145 DIV(0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4),
146 DIV(0, "div_mmc1", "mout_mmc1", DIV_FSYS1, 16, 4),
150 DIV_FSYS1, 8, 8, CLK_SET_RATE_PARENT, 0),
152 DIV_FSYS1, 24, 8, CLK_SET_RATE_PARENT, 0),
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| H A D | clk-exynos5250.c | 65 #define DIV_FSYS1 0x1054c macro
149 DIV_FSYS1,
395 DIV(0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4),
397 DIV_FSYS1, 8, 8, CLK_SET_RATE_PARENT, 0),
398 DIV(0, "div_mmc1", "mout_mmc1", DIV_FSYS1, 16, 4),
400 DIV_FSYS1, 24, 8, CLK_SET_RATE_PARENT, 0),
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| H A D | clk-exynos3250.c | 57 #define DIV_FSYS1 0xc544 macro
146 DIV_FSYS1,
388 /* DIV_FSYS1 */
389 DIV_F(CLK_DIV_MMC1_PRE, "div_mmc1_pre", "div_mmc1", DIV_FSYS1, 24, 8,
391 DIV(CLK_DIV_MMC1, "div_mmc1", "mout_mmc1", DIV_FSYS1, 16, 4),
392 DIV_F(CLK_DIV_MMC0_PRE, "div_mmc0_pre", "div_mmc0", DIV_FSYS1, 8, 8,
394 DIV(CLK_DIV_MMC0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4),
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| H A D | clk-exynos4.c | 76 #define DIV_FSYS1 0xc544 macro
227 DIV_FSYS1,
629 DIV(0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4),
630 DIV(0, "div_mmc1", "mout_mmc1", DIV_FSYS1, 16, 4),
662 DIV_F(0, "div_mmc_pre0", "div_mmc0", DIV_FSYS1, 8, 8,
664 DIV_F(0, "div_mmc_pre1", "div_mmc1", DIV_FSYS1, 24, 8,
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| H A D | clk-exynos7.c | 989 #define DIV_FSYS1 0x0600 macro
1023 DIV_FSYS1,
1056 DIV_FSYS1, 0, 2),
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| H A D | clk-exynos5420.c | 90 #define DIV_FSYS1 0x1054c macro
219 DIV_FSYS1,
873 DIV(0, "dout_mmc0", "mout_mmc0", DIV_FSYS1, 0, 10),
874 DIV(0, "dout_mmc1", "mout_mmc1", DIV_FSYS1, 10, 10),
875 DIV(0, "dout_mmc2", "mout_mmc2", DIV_FSYS1, 20, 10),
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