| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dml/ |
| H A D | display_mode_vba.h | 364 unsigned int PrefetchMode[DC__VOLTAGE_STATES][2];
365 unsigned int PrefetchModePerState[DC__VOLTAGE_STATES][2];
413 double DCFCLKPerState[DC__VOLTAGE_STATES];
414 double DCFCLKState[DC__VOLTAGE_STATES][2];
415 double FabricClockPerState[DC__VOLTAGE_STATES];
416 double SOCCLKPerState[DC__VOLTAGE_STATES];
417 double PHYCLKPerState[DC__VOLTAGE_STATES];
418 double DTBCLKPerState[DC__VOLTAGE_STATES];
419 double MaxDppclk[DC__VOLTAGE_STATES];
420 double MaxDSCCLK[DC__VOLTAGE_STATES];
[all...] |
| H A D | display_mode_structs.h | 73 struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES];
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| H A D | dc_features.h | 32 #define DC__VOLTAGE_STATES 9 macro
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| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dml/ |
| H A D | display_mode_vba.h | 317 double ActiveDRAMClockChangeLatencyMarginPerState[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];// DML doesn't save active margin per state
536 unsigned int PrefetchMode[DC__VOLTAGE_STATES][2];
537 unsigned int PrefetchModePerState[DC__VOLTAGE_STATES][2];
599 double DCFCLKPerState[DC__VOLTAGE_STATES];
600 double DCFCLKState[DC__VOLTAGE_STATES][2];
601 double FabricClockPerState[DC__VOLTAGE_STATES];
602 double SOCCLKPerState[DC__VOLTAGE_STATES];
603 double PHYCLKPerState[DC__VOLTAGE_STATES];
604 double DTBCLKPerState[DC__VOLTAGE_STATES];
605 double MaxDppclk[DC__VOLTAGE_STATES];
[all...] |
| H A D | dc_features.h | 34 * @DC__VOLTAGE_STATES:
39 #define DC__VOLTAGE_STATES 40 macro
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| H A D | display_mode_structs.h | 182 struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES];
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| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dml/dcn302/ |
| H A D | dcn302_fpu.c | 200 unsigned int dcfclk_mhz[DC__VOLTAGE_STATES] = {0}; in dcn302_fpu_update_bw_bounding_box()
201 unsigned int dram_speed_mts[DC__VOLTAGE_STATES] = {0}; in dcn302_fpu_update_bw_bounding_box()
202 unsigned int optimal_uclk_for_dcfclk_sta_targets[DC__VOLTAGE_STATES] = {0}; in dcn302_fpu_update_bw_bounding_box()
203 unsigned int optimal_dcfclk_for_uclk[DC__VOLTAGE_STATES] = {0}; in dcn302_fpu_update_bw_bounding_box()
205 unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {694, 875, 1000, 1200}; in dcn302_fpu_update_bw_bounding_box()
282 while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) { in dcn302_fpu_update_bw_bounding_box()
296 while (i < num_dcfclk_sta_targets && num_states < DC__VOLTAGE_STATES) { in dcn302_fpu_update_bw_bounding_box()
301 while (j < num_uclk_states && num_states < DC__VOLTAGE_STATES && in dcn302_fpu_update_bw_bounding_box()
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| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dml/dcn303/ |
| H A D | dcn303_fpu.c | 196 unsigned int dcfclk_mhz[DC__VOLTAGE_STATES] = {0}; in dcn303_fpu_update_bw_bounding_box()
197 unsigned int dram_speed_mts[DC__VOLTAGE_STATES] = {0}; in dcn303_fpu_update_bw_bounding_box()
198 unsigned int optimal_uclk_for_dcfclk_sta_targets[DC__VOLTAGE_STATES] = {0}; in dcn303_fpu_update_bw_bounding_box()
199 unsigned int optimal_dcfclk_for_uclk[DC__VOLTAGE_STATES] = {0}; in dcn303_fpu_update_bw_bounding_box()
201 unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {694, 875, 1000, 1200}; in dcn303_fpu_update_bw_bounding_box()
276 while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) { in dcn303_fpu_update_bw_bounding_box()
291 while (i < num_dcfclk_sta_targets && num_states < DC__VOLTAGE_STATES) { in dcn303_fpu_update_bw_bounding_box()
296 while (j < num_uclk_states && num_states < DC__VOLTAGE_STATES && in dcn303_fpu_update_bw_bounding_box()
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| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dml/dcn321/ |
| H A D | dcn321_fpu.c | 354 unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {199, 615, 906, 1324, 1564}; in build_synthetic_soc_states()
698 unsigned int dcfclk_mhz[DC__VOLTAGE_STATES] = {0}; in dcn321_update_bw_bounding_box_fpu()
699 unsigned int dram_speed_mts[DC__VOLTAGE_STATES] = {0}; in dcn321_update_bw_bounding_box_fpu()
700 unsigned int optimal_uclk_for_dcfclk_sta_targets[DC__VOLTAGE_STATES] = {0}; in dcn321_update_bw_bounding_box_fpu()
701 unsigned int optimal_dcfclk_for_uclk[DC__VOLTAGE_STATES] = {0}; in dcn321_update_bw_bounding_box_fpu()
703 unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {615, 906, 1324, 1564}; in dcn321_update_bw_bounding_box_fpu()
767 while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) { in dcn321_update_bw_bounding_box_fpu()
781 while (i < num_dcfclk_sta_targets && num_states < DC__VOLTAGE_STATES) { in dcn321_update_bw_bounding_box_fpu()
786 while (j < num_uclk_states && num_states < DC__VOLTAGE_STATES && in dcn321_update_bw_bounding_box_fpu()
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| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn30/ |
| H A D | dcn30_resource.c | 2094 unsigned int dcfclk_mhz[DC__VOLTAGE_STATES] = {0}; in dcn30_update_bw_bounding_box()
2095 unsigned int dram_speed_mts[DC__VOLTAGE_STATES] = {0}; in dcn30_update_bw_bounding_box()
2096 unsigned int optimal_uclk_for_dcfclk_sta_targets[DC__VOLTAGE_STATES] = {0}; in dcn30_update_bw_bounding_box()
2097 unsigned int optimal_dcfclk_for_uclk[DC__VOLTAGE_STATES] = {0}; in dcn30_update_bw_bounding_box()
2099 unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {694, 875, 1000, 1200}; in dcn30_update_bw_bounding_box()
2174 while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) { in dcn30_update_bw_bounding_box()
2188 while (i < num_dcfclk_sta_targets && num_states < DC__VOLTAGE_STATES) { in dcn30_update_bw_bounding_box()
2193 while (j < num_uclk_states && num_states < DC__VOLTAGE_STATES && in dcn30_update_bw_bounding_box()
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| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dcn30/ |
| H A D | dcn30_resource.c | 2464 unsigned int dcfclk_mhz[DC__VOLTAGE_STATES] = {0}; in dcn30_update_bw_bounding_box()
2465 unsigned int dram_speed_mts[DC__VOLTAGE_STATES] = {0}; in dcn30_update_bw_bounding_box()
2466 unsigned int optimal_uclk_for_dcfclk_sta_targets[DC__VOLTAGE_STATES] = {0}; in dcn30_update_bw_bounding_box()
2467 unsigned int optimal_dcfclk_for_uclk[DC__VOLTAGE_STATES] = {0}; in dcn30_update_bw_bounding_box()
2469 unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {694, 875, 1000, 1200}; in dcn30_update_bw_bounding_box()
2548 while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) { in dcn30_update_bw_bounding_box()
2562 while (i < num_dcfclk_sta_targets && num_states < DC__VOLTAGE_STATES) { in dcn30_update_bw_bounding_box()
2567 while (j < num_uclk_states && num_states < DC__VOLTAGE_STATES && in dcn30_update_bw_bounding_box()
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| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dml/dcn32/ |
| H A D | dcn32_fpu.c | 2458 unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {199, 615, 906, 1324, 1564}; in build_synthetic_soc_states()
2787 unsigned int dcfclk_mhz[DC__VOLTAGE_STATES] = {0}; in dcn32_update_bw_bounding_box_fpu()
2788 unsigned int dram_speed_mts[DC__VOLTAGE_STATES] = {0}; in dcn32_update_bw_bounding_box_fpu()
2789 unsigned int optimal_uclk_for_dcfclk_sta_targets[DC__VOLTAGE_STATES] = {0}; in dcn32_update_bw_bounding_box_fpu()
2790 unsigned int optimal_dcfclk_for_uclk[DC__VOLTAGE_STATES] = {0}; in dcn32_update_bw_bounding_box_fpu()
2794 unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {199, 615, 906, 1324, 1564}; in dcn32_update_bw_bounding_box_fpu()
2863 while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) { in dcn32_update_bw_bounding_box_fpu()
2877 while (i < num_dcfclk_sta_targets && num_states < DC__VOLTAGE_STATES) { in dcn32_update_bw_bounding_box_fpu()
2882 while (j < num_uclk_states && num_states < DC__VOLTAGE_STATES && in dcn32_update_bw_bounding_box_fpu()
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| H A D | display_mode_vba_util_32.c | 2982 double TotalMaxPrefetchFlipDPTERowBandwidth[DC__VOLTAGE_STATES][2]; in dml32_UseMinimumDCFCLK()
2985 for (i = 0; i < DC__VOLTAGE_STATES; ++i) { in dml32_UseMinimumDCFCLK()
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| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/ |
| H A D | dc.h | 987 struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES];
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| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dcn21/ |
| H A D | dcn21_resource.c | 1407 struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES]; in update_bw_bounding_box()
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| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dcn20/ |
| H A D | dcn20_resource.c | 3489 struct _vcs_dpi_voltage_scaling_st calculated_states[DC__VOLTAGE_STATES];
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| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dml/dcn30/ |
| H A D | display_mode_vba_30.c | 6722 double TotalMaxPrefetchFlipDPTERowBandwidth[DC__VOLTAGE_STATES][2] = { { 0 } }; in UseMinimumDCFCLK()
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| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dml/dcn30/ |
| H A D | display_mode_vba_30.c | 6503 double TotalMaxPrefetchFlipDPTERowBandwidth[DC__VOLTAGE_STATES][2] = { { 0 } }; in UseMinimumDCFCLK()
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| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
| H A D | display_mode_vba_31.c | 7045 double TotalMaxPrefetchFlipDPTERowBandwidth[DC__VOLTAGE_STATES][2];
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| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dml/dcn314/ |
| H A D | display_mode_vba_314.c | 7133 double TotalMaxPrefetchFlipDPTERowBandwidth[DC__VOLTAGE_STATES][2];
|