Searched refs:DCC (Results 1 - 14 of 14) sorted by relevance
| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/amdgpu_dm/ |
| H A D | amdgpu_dm_plane.c | 169 return IS_AMD_FMT_MOD(modifier) && AMD_FMT_MOD_GET(DCC, modifier); in modifier_has_dcc()
257 /* for DCC we know it isn't rb aligned, so rb_per_se doesn't matter. */ in fill_gfx9_tiling_info_from_modifier()
366 AMD_FMT_MOD_SET(DCC, 1) | in add_gfx10_1_modifiers()
375 AMD_FMT_MOD_SET(DCC, 1) | in add_gfx10_1_modifiers()
419 * No _D DCC swizzles yet because we only allow 32bpp, which in add_gfx9_modifiers()
429 AMD_FMT_MOD_SET(DCC, 1) | in add_gfx9_modifiers()
440 AMD_FMT_MOD_SET(DCC, 1) | in add_gfx9_modifiers()
451 AMD_FMT_MOD_SET(DCC, 1) | in add_gfx9_modifiers()
466 AMD_FMT_MOD_SET(DCC, 1) | in add_gfx9_modifiers()
519 AMD_FMT_MOD_SET(DCC, in add_gfx10_3_modifiers()
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| /kernel/linux/linux-5.10/arch/arm/include/debug/ |
| H A D | tegra.S | 85 cmp \rv, #2 @ 2 and 3 mean DCC, UART
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| /kernel/linux/linux-6.6/arch/arm/include/debug/ |
| H A D | tegra.S | 85 cmp \rv, #2 @ 2 and 3 mean DCC, UART
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| /kernel/linux/linux-6.6/drivers/gpu/drm/i915/ |
| H A D | intel_mchbar_regs.h | 36 #define DCC _MMIO(MCHBAR_MIRROR_BASE + 0x200) macro
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| H A D | i915_debugfs.c | 458 intel_uncore_read(uncore, DCC)); in i915_swizzle_info()
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| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/amdgpu/ |
| H A D | amdgpu_display.c | 662 if (AMD_FMT_MOD_GET(DCC, modifier)) in amdgpu_lookup_format_info()
672 * Tries to extract the renderable DCC offset from the opaque metadata attached
847 modifier |= AMD_FMT_MOD_SET(DCC, 1) | in convert_tiling_flags_to_modifier()
859 * info on the renderable DCC buffer. Luckily the opaque metadata contains in convert_tiling_flags_to_modifier()
862 * userspace driver that gets it doesn't have to juggle around another DCC in convert_tiling_flags_to_modifier()
1072 if (AMD_FMT_MOD_GET(DCC, modifier)) { in amdgpu_display_verify_sizes()
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| /kernel/linux/linux-5.10/drivers/atm/ |
| H A D | he.h | 657 #define DCC 0x807cc macro
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| H A D | he.c | 1410 he_writel(he_dev, 0x0, DCC); in he_start()
2730 dcc += he_readl(he_dev, DCC); in he_proc_read()
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| /kernel/linux/linux-5.10/drivers/gpu/drm/i915/gt/ |
| H A D | intel_ggtt_fencing.c | 661 u32 dcc = intel_uncore_read(uncore, DCC); in detect_bit_6_swizzle()
665 * determined by DCC. For single-channel, neither the CPU in detect_bit_6_swizzle()
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| /kernel/linux/linux-6.6/drivers/atm/ |
| H A D | he.h | 657 #define DCC 0x807cc macro
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| H A D | he.c | 1407 he_writel(he_dev, 0x0, DCC); in he_start()
2727 dcc += he_readl(he_dev, DCC); in he_proc_read()
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| /kernel/linux/linux-6.6/drivers/gpu/drm/i915/gt/ |
| H A D | intel_ggtt_fencing.c | 668 u32 dcc = intel_uncore_read(uncore, DCC); in detect_bit_6_swizzle()
672 * determined by DCC. For single-channel, neither the CPU in detect_bit_6_swizzle()
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| /kernel/linux/linux-5.10/drivers/gpu/drm/i915/ |
| H A D | i915_debugfs.c | 1166 intel_uncore_read(uncore, DCC)); in i915_swizzle_info()
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| H A D | i915_reg.h | 3763 #define DCC _MMIO(MCHBAR_MIRROR_BASE + 0x200) macro
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