Home
last modified time | relevance | path

Searched refs:CVMX_CACHE_LINE_SIZE (Results 1 - 8 of 8) sorted by relevance

/kernel/linux/linux-5.10/arch/mips/include/asm/octeon/
H A Dcvmx-config.h24 #define CVMX_FPA_POOL_0_SIZE (16 * CVMX_CACHE_LINE_SIZE)
25 #define CVMX_FPA_POOL_1_SIZE (1 * CVMX_CACHE_LINE_SIZE)
26 #define CVMX_FPA_POOL_2_SIZE (8 * CVMX_CACHE_LINE_SIZE)
27 #define CVMX_FPA_POOL_3_SIZE (0 * CVMX_CACHE_LINE_SIZE)
28 #define CVMX_FPA_POOL_4_SIZE (0 * CVMX_CACHE_LINE_SIZE)
29 #define CVMX_FPA_POOL_5_SIZE (0 * CVMX_CACHE_LINE_SIZE)
30 #define CVMX_FPA_POOL_6_SIZE (0 * CVMX_CACHE_LINE_SIZE)
31 #define CVMX_FPA_POOL_7_SIZE (0 * CVMX_CACHE_LINE_SIZE)
H A Dcvmx.h87 #define CVMX_CACHE_LINE_SIZE (128) /* In bytes */ macro
88 #define CVMX_CACHE_LINE_MASK (CVMX_CACHE_LINE_SIZE - 1) /* In bytes */
89 #define CVMX_CACHE_LINE_ALIGNED __attribute__ ((aligned(CVMX_CACHE_LINE_SIZE)))
/kernel/linux/linux-6.6/arch/mips/include/asm/octeon/
H A Dcvmx-config.h24 #define CVMX_FPA_POOL_0_SIZE (16 * CVMX_CACHE_LINE_SIZE)
25 #define CVMX_FPA_POOL_1_SIZE (1 * CVMX_CACHE_LINE_SIZE)
26 #define CVMX_FPA_POOL_2_SIZE (8 * CVMX_CACHE_LINE_SIZE)
27 #define CVMX_FPA_POOL_3_SIZE (0 * CVMX_CACHE_LINE_SIZE)
28 #define CVMX_FPA_POOL_4_SIZE (0 * CVMX_CACHE_LINE_SIZE)
29 #define CVMX_FPA_POOL_5_SIZE (0 * CVMX_CACHE_LINE_SIZE)
30 #define CVMX_FPA_POOL_6_SIZE (0 * CVMX_CACHE_LINE_SIZE)
31 #define CVMX_FPA_POOL_7_SIZE (0 * CVMX_CACHE_LINE_SIZE)
H A Dcvmx.h87 #define CVMX_CACHE_LINE_SIZE (128) /* In bytes */ macro
88 #define CVMX_CACHE_LINE_MASK (CVMX_CACHE_LINE_SIZE - 1) /* In bytes */
89 #define CVMX_CACHE_LINE_ALIGNED __attribute__ ((aligned(CVMX_CACHE_LINE_SIZE)))
/kernel/linux/linux-5.10/drivers/mmc/host/
H A Dcavium-octeon.c63 end = ALIGN(start + len - 1, CVMX_CACHE_LINE_SIZE); in l2c_lock_mem_region()
64 start = ALIGN(start, CVMX_CACHE_LINE_SIZE); in l2c_lock_mem_region()
68 start += CVMX_CACHE_LINE_SIZE; in l2c_lock_mem_region()
79 end = ALIGN(start + len - 1, CVMX_CACHE_LINE_SIZE); in l2c_unlock_mem_region()
80 start = ALIGN(start, CVMX_CACHE_LINE_SIZE); in l2c_unlock_mem_region()
84 start += CVMX_CACHE_LINE_SIZE; in l2c_unlock_mem_region()
/kernel/linux/linux-6.6/drivers/mmc/host/
H A Dcavium-octeon.c65 end = ALIGN(start + len - 1, CVMX_CACHE_LINE_SIZE); in l2c_lock_mem_region()
66 start = ALIGN(start, CVMX_CACHE_LINE_SIZE); in l2c_lock_mem_region()
70 start += CVMX_CACHE_LINE_SIZE; in l2c_lock_mem_region()
81 end = ALIGN(start + len - 1, CVMX_CACHE_LINE_SIZE); in l2c_unlock_mem_region()
82 start = ALIGN(start, CVMX_CACHE_LINE_SIZE); in l2c_unlock_mem_region()
86 start += CVMX_CACHE_LINE_SIZE; in l2c_unlock_mem_region()
/kernel/linux/linux-5.10/arch/mips/cavium-octeon/executive/
H A Dcvmx-l2c.c309 len -= CVMX_CACHE_LINE_SIZE; in fault_in()
310 ptr += CVMX_CACHE_LINE_SIZE; in fault_in()
394 fault_in(addr, CVMX_CACHE_LINE_SIZE); in cvmx_l2c_lock_line()
425 start += CVMX_CACHE_LINE_SIZE; in cvmx_l2c_lock_mem_region()
426 len -= CVMX_CACHE_LINE_SIZE; in cvmx_l2c_lock_mem_region()
515 start += CVMX_CACHE_LINE_SIZE; in cvmx_l2c_unlock_mem_region()
516 len -= CVMX_CACHE_LINE_SIZE; in cvmx_l2c_unlock_mem_region()
764 CVMX_CACHE_LINE_SIZE; in cvmx_l2c_get_cache_size_bytes()
912 index * CVMX_CACHE_LINE_SIZE), in cvmx_l2c_flush_line()
/kernel/linux/linux-6.6/arch/mips/cavium-octeon/executive/
H A Dcvmx-l2c.c309 len -= CVMX_CACHE_LINE_SIZE; in fault_in()
310 ptr += CVMX_CACHE_LINE_SIZE; in fault_in()
394 fault_in(addr, CVMX_CACHE_LINE_SIZE); in cvmx_l2c_lock_line()
425 start += CVMX_CACHE_LINE_SIZE; in cvmx_l2c_lock_mem_region()
426 len -= CVMX_CACHE_LINE_SIZE; in cvmx_l2c_lock_mem_region()
515 start += CVMX_CACHE_LINE_SIZE; in cvmx_l2c_unlock_mem_region()
516 len -= CVMX_CACHE_LINE_SIZE; in cvmx_l2c_unlock_mem_region()
764 CVMX_CACHE_LINE_SIZE; in cvmx_l2c_get_cache_size_bytes()
911 index * CVMX_CACHE_LINE_SIZE), in cvmx_l2c_flush_line()

Completed in 6 milliseconds