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Searched refs:CP_RB0_CNTL (Results 1 - 21 of 21) sorted by relevance

/kernel/linux/linux-5.10/drivers/gpu/drm/radeon/
H A Dnid.h484 #define CP_RB0_CNTL 0xC104 macro
H A Dcikd.h1302 #define CP_RB0_CNTL 0xC104 macro
H A Dsid.h1246 #define CP_RB0_CNTL 0xC104 macro
H A Dsi.c3678 WREG32(CP_RB0_CNTL, tmp); in si_cp_resume()
3681 WREG32(CP_RB0_CNTL, tmp | RB_RPTR_WR_ENA); in si_cp_resume()
3697 WREG32(CP_RB0_CNTL, tmp); in si_cp_resume()
H A Dni.c1632 CP_RB0_CNTL, in cayman_cp_resume()
H A Dcik.c4084 WREG32(CP_RB0_CNTL, tmp); in cik_cp_gfx_resume()
4087 WREG32(CP_RB0_CNTL, tmp | RB_RPTR_WR_ENA); in cik_cp_gfx_resume()
4102 WREG32(CP_RB0_CNTL, tmp); in cik_cp_gfx_resume()
4667 /* set up the HQD, this is similar to CP_RB0_CNTL */ in cik_cp_compute_resume()
/kernel/linux/linux-6.6/drivers/gpu/drm/radeon/
H A Dnid.h484 #define CP_RB0_CNTL 0xC104 macro
H A Dcikd.h1302 #define CP_RB0_CNTL 0xC104 macro
H A Dsid.h1246 #define CP_RB0_CNTL 0xC104 macro
H A Dsi.c3673 WREG32(CP_RB0_CNTL, tmp); in si_cp_resume()
3676 WREG32(CP_RB0_CNTL, tmp | RB_RPTR_WR_ENA); in si_cp_resume()
3692 WREG32(CP_RB0_CNTL, tmp); in si_cp_resume()
H A Dni.c1619 CP_RB0_CNTL, in cayman_cp_resume()
H A Dcik.c4074 WREG32(CP_RB0_CNTL, tmp); in cik_cp_gfx_resume()
4077 WREG32(CP_RB0_CNTL, tmp | RB_RPTR_WR_ENA); in cik_cp_gfx_resume()
4092 WREG32(CP_RB0_CNTL, tmp); in cik_cp_gfx_resume()
4657 /* set up the HQD, this is similar to CP_RB0_CNTL */ in cik_cp_compute_resume()
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v8_0.c4286 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); in gfx_v8_0_cp_gfx_resume()
4287 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); in gfx_v8_0_cp_gfx_resume()
4288 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, MTYPE, 3); in gfx_v8_0_cp_gfx_resume()
4289 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, MIN_IB_AVAILSZ, 1); in gfx_v8_0_cp_gfx_resume()
4291 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1); in gfx_v8_0_cp_gfx_resume()
4497 /* set up the HQD, this is similar to CP_RB0_CNTL */ in gfx_v8_0_mqd_init()
H A Dsid.h1274 #define CP_RB0_CNTL 0x3041 macro
H A Dgfx_v9_0.c3277 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); in gfx_v9_0_cp_gfx_resume()
3278 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); in gfx_v9_0_cp_gfx_resume()
3280 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1); in gfx_v9_0_cp_gfx_resume()
3492 /* set up the HQD, this is similar to CP_RB0_CNTL */ in gfx_v9_0_mqd_init()
3620 /* set up the HQD, this is similar to CP_RB0_CNTL */ in gfx_v9_0_kiq_init_register()
H A Dgfx_v10_0.c5907 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); in gfx_v10_0_cp_gfx_resume()
5908 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); in gfx_v10_0_cp_gfx_resume()
5910 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1); in gfx_v10_0_cp_gfx_resume()
6178 /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */ in gfx_v10_0_gfx_mqd_init()
6442 /* set up the HQD, this is similar to CP_RB0_CNTL */ in gfx_v10_0_compute_mqd_init()
6574 /* set up the HQD, this is similar to CP_RB0_CNTL */ in gfx_v10_0_kiq_init_register()
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v8_0.c4253 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); in gfx_v8_0_cp_gfx_resume()
4254 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); in gfx_v8_0_cp_gfx_resume()
4255 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, MTYPE, 3); in gfx_v8_0_cp_gfx_resume()
4256 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, MIN_IB_AVAILSZ, 1); in gfx_v8_0_cp_gfx_resume()
4258 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1); in gfx_v8_0_cp_gfx_resume()
4462 /* set up the HQD, this is similar to CP_RB0_CNTL */ in gfx_v8_0_mqd_init()
H A Dsid.h1274 #define CP_RB0_CNTL 0x3041 macro
H A Dgfx_v9_0.c3109 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); in gfx_v9_0_cp_gfx_resume()
3110 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); in gfx_v9_0_cp_gfx_resume()
3112 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1); in gfx_v9_0_cp_gfx_resume()
3321 /* set up the HQD, this is similar to CP_RB0_CNTL */ in gfx_v9_0_mqd_init()
3432 /* set up the HQD, this is similar to CP_RB0_CNTL */ in gfx_v9_0_kiq_init_register()
H A Dgfx_v11_0.c3258 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); in gfx_v11_0_cp_gfx_resume()
3259 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); in gfx_v11_0_cp_gfx_resume()
3650 /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */ in gfx_v11_0_gfx_mqd_init()
3804 /* set up the HQD, this is similar to CP_RB0_CNTL */ in gfx_v11_0_compute_mqd_init()
3929 /* set up the HQD, this is similar to CP_RB0_CNTL */ in gfx_v11_0_kiq_init_register()
H A Dgfx_v10_0.c6102 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); in gfx_v10_0_cp_gfx_resume()
6103 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); in gfx_v10_0_cp_gfx_resume()
6105 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1); in gfx_v10_0_cp_gfx_resume()
6401 /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */ in gfx_v10_0_gfx_mqd_init()
6564 /* set up the HQD, this is similar to CP_RB0_CNTL */ in gfx_v10_0_compute_mqd_init()
6674 /* set up the HQD, this is similar to CP_RB0_CNTL */ in gfx_v10_0_kiq_init_register()

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