Searched refs:CP_ME1_PIPE0_INT_CNTL (Results 1 - 12 of 12) sorted by relevance
| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/amdgpu/ |
| H A D | gfx_v11_0.c | 5798 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, in gfx_v11_0_set_compute_eop_interrupt_state()
5800 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, in gfx_v11_0_set_compute_eop_interrupt_state()
5806 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, in gfx_v11_0_set_compute_eop_interrupt_state()
5808 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, in gfx_v11_0_set_compute_eop_interrupt_state()
6024 tmp = REG_SET_FIELD(tmp, CP_ME1_PIPE0_INT_CNTL,
6034 tmp = REG_SET_FIELD(tmp, CP_ME1_PIPE0_INT_CNTL,
|
| H A D | gfx_v9_4_3.c | 2742 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, in gfx_v9_4_3_xcc_set_compute_eop_interrupt_state()
2748 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, in gfx_v9_4_3_xcc_set_compute_eop_interrupt_state()
|
| H A D | gfx_v9_0.c | 5764 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, in gfx_v9_0_set_compute_eop_interrupt_state()
5770 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, in gfx_v9_0_set_compute_eop_interrupt_state()
|
| H A D | gfx_v10_0.c | 8841 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, in gfx_v10_0_set_compute_eop_interrupt_state()
8847 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, in gfx_v10_0_set_compute_eop_interrupt_state()
|
| H A D | gfx_v8_0.c | 6554 WREG32_FIELD(CP_ME1_PIPE0_INT_CNTL, CP_ECC_ERROR_INT_ENABLE, in gfx_v8_0_set_cp_ecc_int_state()
|
| /kernel/linux/linux-5.10/drivers/gpu/drm/radeon/ |
| H A D | cikd.h | 1358 #define CP_ME1_PIPE0_INT_CNTL 0xC214 macro
|
| H A D | cik.c | 6879 WREG32(CP_ME1_PIPE0_INT_CNTL, 0); in cik_disable_interrupt_state()
7062 cp_m1p0 = RREG32(CP_ME1_PIPE0_INT_CNTL) & ~TIME_STAMP_INT_ENABLE; in cik_irq_set()
7233 WREG32(CP_ME1_PIPE0_INT_CNTL, cp_m1p0); in cik_irq_set()
|
| /kernel/linux/linux-6.6/drivers/gpu/drm/radeon/ |
| H A D | cikd.h | 1358 #define CP_ME1_PIPE0_INT_CNTL 0xC214 macro
|
| H A D | cik.c | 6868 WREG32(CP_ME1_PIPE0_INT_CNTL, 0); in cik_disable_interrupt_state()
7051 cp_m1p0 = RREG32(CP_ME1_PIPE0_INT_CNTL) & ~TIME_STAMP_INT_ENABLE; in cik_irq_set()
7222 WREG32(CP_ME1_PIPE0_INT_CNTL, cp_m1p0); in cik_irq_set()
|
| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/amdgpu/ |
| H A D | gfx_v9_0.c | 5697 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, in gfx_v9_0_set_compute_eop_interrupt_state()
5703 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, in gfx_v9_0_set_compute_eop_interrupt_state()
|
| H A D | gfx_v10_0.c | 8288 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, in gfx_v10_0_set_compute_eop_interrupt_state()
8294 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, in gfx_v10_0_set_compute_eop_interrupt_state()
|
| H A D | gfx_v8_0.c | 6582 WREG32_FIELD(CP_ME1_PIPE0_INT_CNTL, CP_ECC_ERROR_INT_ENABLE, in gfx_v8_0_set_cp_ecc_int_state()
|
Completed in 94 milliseconds