CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK (reference) in projects: kernel

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Searched refs:CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK (Results 1 - 25 of 28) sorted by relevance

/kernel/linux/linux-5.10/drivers/gpu/drm/amd/amdgpu/
H A D	gfx_v6_0.c	`3305 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK; in gfx_v6_0_set_priv_reg_fault_state() 3310 cp_int_cntl \|= CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK; in gfx_v6_0_set_priv_reg_fault_state()`
H A D	sid.h	`2431 #define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK 0x800000 macro`
H A D	gfx_v7_0.c	`4802 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK; in gfx_v7_0_set_priv_reg_fault_state() 4807 cp_int_cntl \|= CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK; in gfx_v7_0_set_priv_reg_fault_state()`
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/amdgpu/
H A D	gfx_v6_0.c	`3270 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK; in gfx_v6_0_set_priv_reg_fault_state() 3275 cp_int_cntl \|= CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK; in gfx_v6_0_set_priv_reg_fault_state()`
H A D	sid.h	`2431 #define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK 0x800000 macro`
H A D	gfx_v7_0.c	`4742 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK; in gfx_v7_0_set_priv_reg_fault_state() 4747 cp_int_cntl \|= CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK; in gfx_v7_0_set_priv_reg_fault_state()`
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/gca/
H A D	gfx_6_0_sh_mask.h	`2378 #define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK 0x00800000L macro`
H A D	gfx_8_0_sh_mask.h	`1509 #define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK 0x800000 macro [all...]`
H A D	gfx_7_2_sh_mask.h	`1181 #define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK 0x800000 macro`
H A D	gfx_8_1_sh_mask.h	`2033 #define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK 0x800000 macro [all...]`
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/include/asic_reg/gca/
H A D	gfx_6_0_sh_mask.h	`2378 #define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK 0x00800000L macro`
H A D	gfx_8_0_sh_mask.h	`1509 #define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK 0x800000 macro [all...]`
H A D	gfx_7_2_sh_mask.h	`1181 #define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK 0x800000 macro`
H A D	gfx_8_1_sh_mask.h	`2033 #define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK 0x800000 macro [all...]`
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/gc/
H A D	gc_9_2_1_sh_mask.h	`12291 #define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK global() macro [all...]`
H A D	gc_9_1_sh_mask.h	`12487 #define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK global() macro [all...]`
H A D	gc_9_0_sh_mask.h	`11006 #define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK global() macro [all...]`
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/include/asic_reg/gc/
H A D	gc_9_4_2_sh_mask.h	`2307 #define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK 0x00800000L macro [all...]`
H A D	gc_9_4_3_sh_mask.h	`14016 #define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK global() macro [all...]`
H A D	gc_9_2_1_sh_mask.h	`12291 #define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK global() macro [all...]`
H A D	gc_9_1_sh_mask.h	`12487 #define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK global() macro [all...]`
H A D	gc_9_0_sh_mask.h	`11006 #define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK global() macro [all...]`
H A D	gc_10_3_0_sh_mask.h	`16215 #define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK global() macro [all...]`
H A D	gc_11_0_3_sh_mask.h	`17575 #define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK global() macro [all...]`
H A D	gc_10_1_0_sh_mask.h	`17951 #define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK global() macro [all...]`

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