CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK (reference) in projects: kernel

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Searched refs:CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK (Results 1 - 25 of 28) sorted by relevance

/kernel/linux/linux-5.10/drivers/gpu/drm/amd/amdgpu/
H A D	gfx_v6_0.c	`3330 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK; in gfx_v6_0_set_priv_inst_fault_state() 3335 cp_int_cntl \|= CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK; in gfx_v6_0_set_priv_inst_fault_state()`
H A D	sid.h	`2432 #define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK 0x400000 macro`
H A D	gfx_v7_0.c	`4827 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK; in gfx_v7_0_set_priv_inst_fault_state() 4832 cp_int_cntl \|= CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK; in gfx_v7_0_set_priv_inst_fault_state()`
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/amdgpu/
H A D	gfx_v6_0.c	`3295 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK; in gfx_v6_0_set_priv_inst_fault_state() 3300 cp_int_cntl \|= CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK; in gfx_v6_0_set_priv_inst_fault_state()`
H A D	sid.h	`2432 #define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK 0x400000 macro`
H A D	gfx_v7_0.c	`4767 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK; in gfx_v7_0_set_priv_inst_fault_state() 4772 cp_int_cntl \|= CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK; in gfx_v7_0_set_priv_inst_fault_state()`
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/gca/
H A D	gfx_6_0_sh_mask.h	`2376 #define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK 0x00400000L macro`
H A D	gfx_8_0_sh_mask.h	`1507 #define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK 0x400000 macro [all...]`
H A D	gfx_7_2_sh_mask.h	`1179 #define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK 0x400000 macro`
H A D	gfx_8_1_sh_mask.h	`2031 #define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK 0x400000 macro [all...]`
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/include/asic_reg/gca/
H A D	gfx_6_0_sh_mask.h	`2376 #define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK 0x00400000L macro`
H A D	gfx_8_0_sh_mask.h	`1507 #define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK 0x400000 macro [all...]`
H A D	gfx_7_2_sh_mask.h	`1179 #define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK 0x400000 macro`
H A D	gfx_8_1_sh_mask.h	`2031 #define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK 0x400000 macro [all...]`
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/gc/
H A D	gc_9_2_1_sh_mask.h	`12290 #define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK global() macro [all...]`
H A D	gc_9_1_sh_mask.h	`12486 #define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK global() macro [all...]`
H A D	gc_9_0_sh_mask.h	`11005 #define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK global() macro [all...]`
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/include/asic_reg/gc/
H A D	gc_9_4_2_sh_mask.h	`2306 #define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK 0x00400000L macro [all...]`
H A D	gc_9_4_3_sh_mask.h	`14015 #define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK global() macro [all...]`
H A D	gc_9_2_1_sh_mask.h	`12290 #define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK global() macro [all...]`
H A D	gc_9_1_sh_mask.h	`12486 #define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK global() macro [all...]`
H A D	gc_9_0_sh_mask.h	`11005 #define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK global() macro [all...]`
H A D	gc_10_3_0_sh_mask.h	`16214 #define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK global() macro [all...]`
H A D	gc_11_0_3_sh_mask.h	`17574 #define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK global() macro [all...]`
H A D	gc_10_1_0_sh_mask.h	`17950 #define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK global() macro [all...]`

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