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Searched refs:CP_INT_CNTL_RING0 (Results 1 - 18 of 18) sorted by relevance

/kernel/linux/linux-6.6/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v11_0.c1753 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, in gfx_v11_0_enable_gui_idle_interrupt()
1755 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, in gfx_v11_0_enable_gui_idle_interrupt()
1757 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, in gfx_v11_0_enable_gui_idle_interrupt()
1759 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, in gfx_v11_0_enable_gui_idle_interrupt()
5741 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, in gfx_v11_0_set_gfx_eop_interrupt_state()
5743 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, in gfx_v11_0_set_gfx_eop_interrupt_state()
5749 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, in gfx_v11_0_set_gfx_eop_interrupt_state()
5751 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, in gfx_v11_0_set_gfx_eop_interrupt_state()
5910 WREG32_FIELD15_PREREG(GC, 0, CP_INT_CNTL_RING0, in gfx_v11_0_set_priv_reg_fault_state()
5929 WREG32_FIELD15_PREREG(GC, 0, CP_INT_CNTL_RING0, in gfx_v11_0_set_priv_inst_fault_state()
[all...]
H A Dgfx_v9_0.c2474 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0); in gfx_v9_0_enable_gui_idle_interrupt()
2475 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0); in gfx_v9_0_enable_gui_idle_interrupt()
2476 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0); in gfx_v9_0_enable_gui_idle_interrupt()
2478 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, enable ? 1 : 0); in gfx_v9_0_enable_gui_idle_interrupt()
5717 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, in gfx_v9_0_set_gfx_eop_interrupt_state()
5787 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, in gfx_v9_0_set_priv_reg_fault_state()
5806 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, in gfx_v9_0_set_priv_inst_fault_state()
5832 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, in gfx_v9_0_set_cp_ecc_error_state()
5841 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, in gfx_v9_0_set_cp_ecc_error_state()
H A Dgfx_v8_0.c3858 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0); in gfx_v8_0_enable_gui_idle_interrupt()
3859 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0); in gfx_v8_0_enable_gui_idle_interrupt()
3860 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0); in gfx_v8_0_enable_gui_idle_interrupt()
3861 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, enable ? 1 : 0); in gfx_v8_0_enable_gui_idle_interrupt()
6413 WREG32_FIELD(CP_INT_CNTL_RING0, TIME_STAMP_INT_ENABLE, in gfx_v8_0_set_gfx_eop_interrupt_state()
6473 WREG32_FIELD(CP_INT_CNTL_RING0, PRIV_REG_INT_ENABLE, in gfx_v8_0_set_priv_reg_fault_state()
6484 WREG32_FIELD(CP_INT_CNTL_RING0, PRIV_INSTR_INT_ENABLE, in gfx_v8_0_set_priv_inst_fault_state()
6550 WREG32_FIELD(CP_INT_CNTL_RING0, CP_ECC_ERROR_INT_ENABLE, enable_flag); in gfx_v8_0_set_cp_ecc_int_state()
H A Dgfx_v9_4_3.c1167 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0); in gfx_v9_4_3_xcc_enable_gui_idle_interrupt()
1168 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0); in gfx_v9_4_3_xcc_enable_gui_idle_interrupt()
1169 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0); in gfx_v9_4_3_xcc_enable_gui_idle_interrupt()
2769 WREG32_FIELD15_PREREG(GC, GET_INST(GC, i), CP_INT_CNTL_RING0, in gfx_v9_4_3_set_priv_reg_fault_state()
2792 WREG32_FIELD15_PREREG(GC, GET_INST(GC, i), CP_INT_CNTL_RING0, in gfx_v9_4_3_set_priv_inst_fault_state()
H A Dgfx_v10_0.c5018 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, in gfx_v10_0_enable_gui_idle_interrupt()
5020 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, in gfx_v10_0_enable_gui_idle_interrupt()
5022 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, in gfx_v10_0_enable_gui_idle_interrupt()
5024 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, in gfx_v10_0_enable_gui_idle_interrupt()
8788 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, in gfx_v10_0_set_gfx_eop_interrupt_state()
8794 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, in gfx_v10_0_set_gfx_eop_interrupt_state()
8961 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, in gfx_v10_0_set_priv_reg_fault_state()
8980 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, in gfx_v10_0_set_priv_inst_fault_state()
H A Dsid.h1304 #define CP_INT_CNTL_RING0 0x306A macro
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v9_0.c2656 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0); in gfx_v9_0_enable_gui_idle_interrupt()
2657 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0); in gfx_v9_0_enable_gui_idle_interrupt()
2658 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0); in gfx_v9_0_enable_gui_idle_interrupt()
2659 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, enable ? 1 : 0); in gfx_v9_0_enable_gui_idle_interrupt()
5650 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, in gfx_v9_0_set_gfx_eop_interrupt_state()
5720 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, in gfx_v9_0_set_priv_reg_fault_state()
5739 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, in gfx_v9_0_set_priv_inst_fault_state()
5764 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, in gfx_v9_0_set_cp_ecc_error_state()
5773 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, in gfx_v9_0_set_cp_ecc_error_state()
H A Dgfx_v8_0.c3891 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0); in gfx_v8_0_enable_gui_idle_interrupt()
3892 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0); in gfx_v8_0_enable_gui_idle_interrupt()
3893 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0); in gfx_v8_0_enable_gui_idle_interrupt()
3894 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, enable ? 1 : 0); in gfx_v8_0_enable_gui_idle_interrupt()
6441 WREG32_FIELD(CP_INT_CNTL_RING0, TIME_STAMP_INT_ENABLE, in gfx_v8_0_set_gfx_eop_interrupt_state()
6501 WREG32_FIELD(CP_INT_CNTL_RING0, PRIV_REG_INT_ENABLE, in gfx_v8_0_set_priv_reg_fault_state()
6512 WREG32_FIELD(CP_INT_CNTL_RING0, PRIV_INSTR_INT_ENABLE, in gfx_v8_0_set_priv_inst_fault_state()
6578 WREG32_FIELD(CP_INT_CNTL_RING0, CP_ECC_ERROR_INT_ENABLE, enable_flag); in gfx_v8_0_set_cp_ecc_int_state()
H A Dgfx_v10_0.c4840 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, in gfx_v10_0_enable_gui_idle_interrupt()
4842 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, in gfx_v10_0_enable_gui_idle_interrupt()
4844 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, in gfx_v10_0_enable_gui_idle_interrupt()
4846 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, in gfx_v10_0_enable_gui_idle_interrupt()
8235 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, in gfx_v10_0_set_gfx_eop_interrupt_state()
8241 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, in gfx_v10_0_set_gfx_eop_interrupt_state()
8388 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, in gfx_v10_0_set_priv_reg_fault_state()
8407 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, in gfx_v10_0_set_priv_inst_fault_state()
H A Dsid.h1304 #define CP_INT_CNTL_RING0 0x306A macro
/kernel/linux/linux-5.10/drivers/gpu/drm/radeon/
H A Dsi.c5152 u32 tmp = RREG32(CP_INT_CNTL_RING0); in si_enable_gui_idle_interrupt()
5160 WREG32(CP_INT_CNTL_RING0, tmp); in si_enable_gui_idle_interrupt()
5957 tmp = RREG32(CP_INT_CNTL_RING0) & in si_disable_interrupt_state()
5959 WREG32(CP_INT_CNTL_RING0, tmp); in si_disable_interrupt_state()
6075 cp_int_cntl = RREG32(CP_INT_CNTL_RING0) & in si_irq_set()
6107 WREG32(CP_INT_CNTL_RING0, cp_int_cntl); in si_irq_set()
H A Dcik.c5771 u32 tmp = RREG32(CP_INT_CNTL_RING0); in cik_enable_gui_idle_interrupt()
5777 WREG32(CP_INT_CNTL_RING0, tmp); in cik_enable_gui_idle_interrupt()
6870 tmp = RREG32(CP_INT_CNTL_RING0) & in cik_disable_interrupt_state()
6872 WREG32(CP_INT_CNTL_RING0, tmp); in cik_disable_interrupt_state()
7048 cp_int_cntl = RREG32(CP_INT_CNTL_RING0) & in cik_irq_set()
7228 WREG32(CP_INT_CNTL_RING0, cp_int_cntl); in cik_irq_set()
H A Dcikd.h1331 #define CP_INT_CNTL_RING0 0xC1A8 macro
H A Dsid.h1276 #define CP_INT_CNTL_RING0 0xC1A8 macro
/kernel/linux/linux-6.6/drivers/gpu/drm/radeon/
H A Dsi.c5147 u32 tmp = RREG32(CP_INT_CNTL_RING0); in si_enable_gui_idle_interrupt()
5155 WREG32(CP_INT_CNTL_RING0, tmp); in si_enable_gui_idle_interrupt()
5952 tmp = RREG32(CP_INT_CNTL_RING0) & in si_disable_interrupt_state()
5954 WREG32(CP_INT_CNTL_RING0, tmp); in si_disable_interrupt_state()
6070 cp_int_cntl = RREG32(CP_INT_CNTL_RING0) & in si_irq_set()
6102 WREG32(CP_INT_CNTL_RING0, cp_int_cntl); in si_irq_set()
H A Dcik.c5760 u32 tmp = RREG32(CP_INT_CNTL_RING0); in cik_enable_gui_idle_interrupt()
5766 WREG32(CP_INT_CNTL_RING0, tmp); in cik_enable_gui_idle_interrupt()
6859 tmp = RREG32(CP_INT_CNTL_RING0) & in cik_disable_interrupt_state()
6861 WREG32(CP_INT_CNTL_RING0, tmp); in cik_disable_interrupt_state()
7037 cp_int_cntl = RREG32(CP_INT_CNTL_RING0) & in cik_irq_set()
7217 WREG32(CP_INT_CNTL_RING0, cp_int_cntl); in cik_irq_set()
H A Dcikd.h1331 #define CP_INT_CNTL_RING0 0xC1A8 macro
H A Dsid.h1276 #define CP_INT_CNTL_RING0 0xC1A8 macro

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