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Help
Searched
refs:CPG_PLL0CR
(Results
1 - 8
of
8
) sorted by relevance
/kernel/linux/linux-5.10/drivers/clk/renesas/
H
A
D
clk-r8a73a4.c
28
#define
CPG_PLL0CR
0xd8
macro
96
u32 value = readl(cpg->reg +
CPG_PLL0CR
);
in r8a73a4_cpg_register_clock()
H
A
D
clk-sh73a0.c
30
#define
CPG_PLL0CR
0xd8
macro
97
enable_reg +=
CPG_PLL0CR
;
in sh73a0_cpg_register_clock()
H
A
D
rcar-gen2-cpg.c
24
#define
CPG_PLL0CR
0x00d8
macro
310
u32 pll0cr = readl(base +
CPG_PLL0CR
);
in rcar_gen2_cpg_clk_register()
H
A
D
rcar-gen3-cpg.c
28
#define
CPG_PLL0CR
0x00d8
macro
573
value = readl(base +
CPG_PLL0CR
);
in rcar_gen3_cpg_clk_register()
/kernel/linux/linux-6.6/drivers/clk/renesas/
H
A
D
clk-sh73a0.c
29
#define
CPG_PLL0CR
0xd8
macro
96
enable_reg +=
CPG_PLL0CR
;
in sh73a0_cpg_register_clock()
H
A
D
clk-r8a73a4.c
27
#define
CPG_PLL0CR
0xd8
macro
95
u32 value = readl(base +
CPG_PLL0CR
);
in r8a73a4_cpg_register_clock()
H
A
D
rcar-gen2-cpg.c
24
#define
CPG_PLL0CR
0x00d8
macro
309
u32 pll0cr = readl(base +
CPG_PLL0CR
);
in rcar_gen2_cpg_clk_register()
H
A
D
rcar-gen3-cpg.c
33
#define
CPG_PLL0CR
0x00d8 /* PLLn Control Registers */
macro
373
base, 2,
CPG_PLL0CR
, 0);
in rcar_gen3_cpg_clk_register()
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