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Searched refs:CM_BYPASS (Results 1 - 15 of 15) sorted by relevance

/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dcn30/
H A Ddcn30_dpp_cm.c54 REG_UPDATE(CM_CONTROL, CM_BYPASS, cm_bypass_mode); in dpp3_enable_cm_block()
H A Ddcn30_dpp.h307 TF_SF(CM0_CM_CONTROL, CM_BYPASS, mask_sh), \
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn30/
H A Ddcn30_dpp_cm.c54 REG_UPDATE(CM_CONTROL, CM_BYPASS, cm_bypass_mode); in dpp3_enable_cm_block()
H A Ddcn30_dpp.h312 TF_SF(CM0_CM_CONTROL, CM_BYPASS, mask_sh), \
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dcn10/
H A Ddcn10_dpp_cm.c723 REG_SET(CM_CONTROL, 0, CM_BYPASS, 1); in dpp1_full_bypass()
H A Ddcn10_dpp.h1073 type CM_BYPASS; \
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn10/
H A Ddcn10_dpp_cm.c723 REG_SET(CM_CONTROL, 0, CM_BYPASS, 1); in dpp1_full_bypass()
H A Ddcn10_dpp.h1082 type CM_BYPASS; \
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dcn20/
H A Ddcn20_dpp_cm.c60 REG_UPDATE(CM_CONTROL, CM_BYPASS, cm_bypass_mode); in dpp2_enable_cm_block()
H A Ddcn20_dpp.h550 TF_SF(CM0_CM_CONTROL, CM_BYPASS, mask_sh), \
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn20/
H A Ddcn20_dpp_cm.c60 REG_UPDATE(CM_CONTROL, CM_BYPASS, cm_bypass_mode); in dpp2_enable_cm_block()
H A Ddcn20_dpp.h550 TF_SF(CM0_CM_CONTROL, CM_BYPASS, mask_sh), \
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/include/
H A Dnavi10_enum.h854 * CM_BYPASS enum
857 typedef enum CM_BYPASS { enum
860 } CM_BYPASS; typedef
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/include/
H A Dnavi10_enum.h854 * CM_BYPASS enum
857 typedef enum CM_BYPASS { enum
860 } CM_BYPASS; typedef
H A Dsoc21_enum.h1049 * CM_BYPASS enum
1052 typedef enum CM_BYPASS { enum
1055 } CM_BYPASS; typedef

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