/kernel/linux/linux-5.10/scripts/dtc/include-prefixes/dt-bindings/clock/ |
H A D | mt8135-clk.h | 86 #define CLK_TOP_VENC_SEL 75 macro
|
H A D | mt8173-clk.h | 98 #define CLK_TOP_VENC_SEL 88 macro
|
H A D | mt2712-clk.h | 135 #define CLK_TOP_VENC_SEL 104 macro
|
/kernel/linux/linux-5.10/include/dt-bindings/clock/ |
H A D | mt8135-clk.h | 86 #define CLK_TOP_VENC_SEL 75 macro
|
H A D | mt8173-clk.h | 98 #define CLK_TOP_VENC_SEL 88 macro
|
H A D | mt2712-clk.h | 135 #define CLK_TOP_VENC_SEL 104 macro
|
/kernel/linux/linux-6.6/include/dt-bindings/clock/ |
H A D | mediatek,mt6795-clk.h | 96 #define CLK_TOP_VENC_SEL 85 macro
|
H A D | mt8135-clk.h | 86 #define CLK_TOP_VENC_SEL 75 macro
|
H A D | mt8173-clk.h | 98 #define CLK_TOP_VENC_SEL 88 macro
|
H A D | mt2712-clk.h | 135 #define CLK_TOP_VENC_SEL 104 macro
|
H A D | mt8192-clk.h | 63 #define CLK_TOP_VENC_SEL 51 macro
|
/kernel/linux/linux-6.6/scripts/dtc/include-prefixes/dt-bindings/clock/ |
H A D | mediatek,mt6795-clk.h | 96 #define CLK_TOP_VENC_SEL 85 macro
|
H A D | mt8135-clk.h | 86 #define CLK_TOP_VENC_SEL 75 macro
|
H A D | mt8173-clk.h | 98 #define CLK_TOP_VENC_SEL 88 macro
|
H A D | mt2712-clk.h | 135 #define CLK_TOP_VENC_SEL 104 macro
|
H A D | mt8192-clk.h | 63 #define CLK_TOP_VENC_SEL 51 macro
|
/kernel/linux/linux-6.6/drivers/clk/mediatek/ |
H A D | clk-mt6795-topckgen.c | 462 TOP_MUX_GATE(CLK_TOP_VENC_SEL, "venc_sel", venc_parents, 0x50, 16, 4, 23, 0),
|
H A D | clk-mt8173-topckgen.c | 541 MUX_GATE(CLK_TOP_VENC_SEL, "venc_sel", venc_parents, 0x0050, 16, 4, 23),
|
H A D | clk-mt8135.c | 373 MUX_GATE(CLK_TOP_VENC_SEL, "venc_sel", venc_parents, 0x0150, 8, 3, 15),
|
H A D | clk-mt2712.c | 652 MUX_GATE(CLK_TOP_VENC_SEL, "venc_sel", venc_parents, 0x050, 16, 4, 23),
|
H A D | clk-mt8192.c | 667 MUX_GATE_CLR_SET_UPD(CLK_TOP_VENC_SEL, "venc_sel",
|
/kernel/linux/linux-5.10/drivers/clk/mediatek/ |
H A D | clk-mt8135.c | 371 MUX_GATE(CLK_TOP_VENC_SEL, "venc_sel", venc_parents, 0x0150, 8, 3, 15),
|
H A D | clk-mt8173.c | 549 MUX_GATE(CLK_TOP_VENC_SEL, "venc_sel", venc_parents, 0x0050, 16, 4, 23),
|
H A D | clk-mt2712.c | 749 MUX_GATE(CLK_TOP_VENC_SEL, "venc_sel",
|