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Searched refs:CLK_TOP_PE2_MAC_P1_SEL (Results 1 - 6 of 6) sorted by relevance

/kernel/linux/linux-5.10/scripts/dtc/include-prefixes/dt-bindings/clock/
H A Dmt2712-clk.h163 #define CLK_TOP_PE2_MAC_P1_SEL 132 macro
/kernel/linux/linux-5.10/include/dt-bindings/clock/
H A Dmt2712-clk.h163 #define CLK_TOP_PE2_MAC_P1_SEL 132 macro
/kernel/linux/linux-6.6/include/dt-bindings/clock/
H A Dmt2712-clk.h163 #define CLK_TOP_PE2_MAC_P1_SEL 132 macro
/kernel/linux/linux-6.6/scripts/dtc/include-prefixes/dt-bindings/clock/
H A Dmt2712-clk.h163 #define CLK_TOP_PE2_MAC_P1_SEL 132 macro
/kernel/linux/linux-6.6/drivers/clk/mediatek/
H A Dclk-mt2712.c698 MUX_GATE(CLK_TOP_PE2_MAC_P1_SEL, "pe2_mac_p1_sel", pe2_mac_p0_parents,
/kernel/linux/linux-5.10/drivers/clk/mediatek/
H A Dclk-mt2712.c812 MUX_GATE(CLK_TOP_PE2_MAC_P1_SEL, "pe2_mac_p1_sel",

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